Test chip circuit for on-chip timing characterization

Details Test chip circuit for on-chip timing characterization Test chip circuit for on-chip timing characterization

1997-05-27

1998-07-28

Canney, Vincent P.

Excavating

G06F 1100

Patent

active

057870926

ABSTRACT:
The inventive system and method determines path delay of at least one test path of logic gates. The invention uses a toggle register to generate a toggling signal, that is sent out onto the path by a launch register. A capture register receives the signal from the other end of the path. A logic gate compares the received signal from a prior launched signal with an inverted launched signal. Since the signal is a toggling signal the prior received signal should be the same as an inverted launched signal. A latch register determines whether the logic gate has detected a match between inverted launched signal and the received signal from a prior launch signal within a predetermined time clock period. As the clock period is shortened, the launched signal will fail to traverse the path and be captured by the capture register within the clock period. This will cause a mis-match in the logic gate. The clock period at the point of mis-match is the delay time of the path. The invention can use two paths to produce a very accurate comparison of the delays on the two paths.

REFERENCES:
patent: 5475830 (1995-12-01), Chen et al.
patent: 5649167 (1997-07-01), Chen et al.

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