Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
1997-12-04
2001-01-09
Fears, Terrell W. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S201000
Reexamination Certificate
active
06172910
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a test cell to analysis a property of the flash EEPROM cell and method of analyzing a property of flash EEPROM cell using same.
2. Description of the Prior Arts
Generally, the flash EEPROM cell is classified into a split gate type and stack gate type. It is desirable that the properties of the split gate type or stack gate type flash EEPROM cell are not changed although the operations of the programming and erasing are repeated and have excellent endurance property. However, the efficiency of the cell may be deteriorated by the repeating operations of the cell. In order to verify the properties of program/erase cycling endurance, a part of main chip cell is changed to a pattern so that the reliability of cell is verified by the pattern. However, the user does not know the degradation while user knows the degree of the degradation.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide the test cell and method of analyzing using the same which can analysis the cause of degradation of flash EEPROM cell in connection with programming, erasing or reading operation.
The test cell according to the present invention comprises a first unit cell consisted of a drain, a source and a floating gate, a control gate; a second unit cell consisted of a drain, a source and a floating gate, control gate formed integrally with the floating gate and control gate of the first unit cell, respectively,; and a third unit cell consisted of a drain, a source and a floating gate, a control gate formed integrally with the floating gate and control gate of the first unit cell, respectively.
A method of analyzing a property of a flash EEPROM cell according to the invention first comprises the steps of; providing a test cell comprising a first unit cell consisted of a drain, a source and a floating gate, a control gate, a second unit cell consisted of a drain, a source and a floating gate, control gate formed integrally with the floating gate and control gate of the first unit cell, respectively, and a third unit cell consisted of a drain, a source and a floating gate, a control gate formed integrally with the floating gate and control gate of the first unit cell, respectively; erasing the first unit cell, whereby the unit cells are erased; reading the unit cells; programming the second unit cell, whereby said unit cells are programmed; reading the unit cells; and performing repeatedly the erasing, reading, programming reading steps as many as predetermined cycles, thereby comparing the unit cells having differ properties, respectively and grasping the cause of lowering the properties.
REFERENCES:
patent: 5590075 (1996-12-01), Mazzali
Fears Terrell W.
Harris, Esq Scott C.
Hyundai Electronics Industries Co,. Ltd.
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