Plastic and nonmetallic article shaping or treating: processes – Mechanical shaping or molding to form or reform shaped article – To produce composite – plural part or multilayered article
Reexamination Certificate
2000-10-02
2003-04-08
Abrams, Neil (Department: 2839)
Plastic and nonmetallic article shaping or treating: processes
Mechanical shaping or molding to form or reform shaped article
To produce composite, plural part or multilayered article
Reexamination Certificate
active
06544461
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to semiconductor manufacture, and more particularly to an improved test carrier for temporarily packaging and testing semiconductor components, such as dice and chip scale packages. This invention also relates to a test system incorporating the carrier, and to a method for fabricating the carrier.
BACKGROUND OF THE INVENTION
Semiconductor components, such as bare dice and chip scale packages must be tested prior to shipment by semiconductor manufacturers. Since these components are relatively small and fragile, carriers have been developed for temporarily packaging the components for testing. The carriers permit electrical connections to be made between external contacts on the components, and testing equipment such as burn-in boards. On bare dice, the external contacts typically comprise planar or bumped bond pads. On chip scale packages, the external contacts typically comprise solder balls in a dense array, such as a ball grid array, or a fine ball grid array.
An interconnect on the carrier includes contacts that make the temporary electrical connections with the external contacts on the components. The interconnect must provide power, ground and signal paths to the component. As the external contacts on the components become smaller and denser, it becomes more difficult to fabricate the carrier with the required number of electrical paths to the interconnect.
Also, the carrier must be reused multiple times in a production environment. Accordingly, it is desirable to make the carrier as damage resistant as possible. Incorporating the interconnect into the carrier, while maintaining a compact outline for the carrier is increasingly difficult. In addition, the fabrication process for the carrier must be capable of producing production quantities at reasonable costs. It would be advantageous to have the capability to fabricate carriers using conventional semiconductor fabrication processes. This would lower initial capital outlays for production equipment, and lower production costs.
In view of the foregoing, improved carriers for testing semiconductor components including unpackaged dice, and chip scale packages are needed. Also needed are improved fabrication processes for carriers. In particular, carriers which can be constructed at low costs, using standard fabrication equipment, are needed.
SUMMARY OF THE INVENTION
In accordance with the present invention, an improved test carrier, and a method for fabricating the carrier, are provided. The test carrier can be used to temporarily package and test semiconductor components, such as bare dice, and chip scale packages.
The test carrier includes a base for retaining one or more components, and a lead frame molded to the base. The lead frame includes lead fingers which form internal signal traces and terminal contacts for the carrier. The carrier also includes an interconnect, which is attached to a mounting paddle of the, lead frame and molded to the base.
The interconnect includes contacts for electrically contacting external contacts on the component under test. The interconnect contacts are electrically connected to the lead fingers of the lead frame by wire bonding. For components with planar external contacts, such as bond pads on bare dice, the interconnect contacts can comprise etched pillars with penetrating projections. Alternately, for planar external contacts, the interconnect contacts can comprise microbumps on a polymer film. For components with bumped contacts, such as chip scale packages having solder balls, the interconnect contacts can comprise recesses, or flat pads, covered with conductive layers.
The carrier also includes a force applying mechanism for biasing the component against the interconnect. The force applying mechanism includes a biasing member, such as a compressible elastomeric spring. The force applying mechanism also includes a lid, and one or more clips, which attach to the carrier base.
In an alternate embodiment, multiple interconnects can be molded to a board having integrally formed clip members. In another alternate embodiment laser machined conductive vias in, the interconnect provide electrical paths for external contacts formed directly on the interconnect.
The method for fabricating the carrier includes the initial step of attaching the interconnect to the lead frame. Following attachment, an elastomeric gasket can be placed on the interconnect and lead frame, to protect the interconnect, and portions of the lead fingers wherein wire bonds will be formed. Alternately, in place of an elastomeric gasket, a polymer layer, such as a thick film resist, can be applied to the interconnect prior to molding. During a molding step, the carrier base is molded to the lead frame and interconnect. Next, the gasket is removed, or the polymer layer is stripped, and the interconnect is wire bonded to the lead fingers. As another alternate wiring bonding can precede molding, and the wire bonds can be encapsulated. Finally, a trim and form step is performed to form exposed portions of the lead fingers into the terminal leads of the carrier.
A test system constructed in accordance with the invention includes the carrier and test circuitry. The test circuitry generates and transmits test signals through the carrier to the component, and evaluates the resultant signals. The test system can also include a burn in board which provides electrical interface between the carrier and test circuitry.
REFERENCES:
patent: 4682270 (1987-07-01), Whitehead et al.
patent: 4815595 (1989-03-01), Bond et al.
patent: 5006792 (1991-04-01), Malhi et al.
patent: 5012386 (1991-04-01), McShane et al.
patent: 5046239 (1991-09-01), Miller et al.
patent: 5073117 (1991-12-01), Malhi et al.
patent: 5088190 (1992-02-01), Malhi et al.
patent: 5123850 (1992-06-01), Elder et al.
patent: 5155067 (1992-10-01), Wood et al.
patent: 5167326 (1992-12-01), Murphy
patent: 5283717 (1994-02-01), Hundt
patent: 5293072 (1994-03-01), Tsuji et al.
patent: 5302891 (1994-04-01), Wood et al.
patent: 5344600 (1994-09-01), McShane et al.
patent: 5360348 (1994-11-01), Johnson
patent: 5367253 (1994-11-01), Wood et al.
patent: 5399903 (1995-03-01), Rostoker et al.
patent: 5400220 (1995-03-01), Swamy
patent: 5408190 (1995-04-01), Wood et al.
patent: 5440240 (1995-08-01), Wood et al.
patent: 5441684 (1995-08-01), Lee
patent: 5451165 (1995-09-01), Cearley-Cabbiness
patent: 5483741 (1996-01-01), Akram et al.
patent: 5495179 (1996-02-01), Wood et al.
patent: 5519332 (1996-05-01), Wood et al.
patent: 5541525 (1996-07-01), Wood et al.
patent: 5543725 (1996-08-01), Lim et al.
patent: 5557145 (1996-09-01), Kobayashi et al.
patent: 5563446 (1996-10-01), Chia et al.
patent: 5568057 (1996-10-01), Kim et al.
patent: 5572140 (1996-11-01), Lim et al.
patent: 5578934 (1996-11-01), Wood et al.
patent: 5607059 (1997-03-01), Kitamura et al.
patent: 5622873 (1997-04-01), Kim et al.
patent: 5633122 (1997-05-01), Tuttle
patent: 5634267 (1997-06-01), Farnworth et al.
patent: 5644247 (1997-07-01), Hyun et al.
patent: 5647121 (1997-07-01), McLellan et al.
patent: 5666064 (1997-09-01), Kasai et al.
patent: 5686317 (1997-11-01), Akram et al.
patent: 5691649 (1997-11-01), Farnworth et al.
patent: 5721496 (1998-02-01), Farnworth et al.
patent: 5739050 (1998-04-01), Farnworth
patent: 5742169 (1998-04-01), Akram et al.
patent: D394844 (1998-06-01), Farnworth et al.
patent: 5783461 (1998-07-01), Hembree
patent: 5796264 (1998-08-01), Farnworth et al.
patent: 5815000 (1998-09-01), Farnworth
patent: 5825195 (1998-10-01), Hembree et al.
patent: 5834945 (1998-11-01), Akram et al.
patent: 5844418 (1998-12-01), Wood et al.
patent: 5878485 (1999-03-01), Wood et al.
patent: 5896036 (1999-04-01), Wood et al.
patent: 5915977 (1999-06-01), Hembree et al.
patent: 5929647 (1999-07-01), Akram et al.
patent: 5931685 (1999-08-01), Hembree et al.
patent: 5962921 (1999-10-01), Farnworth et al.
patent: 5982185 (1999-11-01), Farnworth
patent: 6016060 (2000-01-01), Akram et al.
patent: 6018249 (2000-01-01), Akram et al.
patent: 6025728 (2000-02-01), Hemb
Ahmad Syed Sajid
Akram Salman
Farnworth Warren M.
Gochnour Derek
Hembree David R.
Abrams Neil
Gratton Stephen A.
Micro)n Technology, Inc.
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