Test board for testing a semiconductor device utilizing...

Details Test board for testing a semiconductor device utilizing... Test board for testing a semiconductor device utilizing...

1998-09-03

2002-03-12

Karlsen, Ernest (Department: 2858)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

Reexamination Certificate

active

06356096

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a circuit structure of an internal input/output (I/O) buffer achieving a high-precision timing verification test of a semiconductor device (hereinafter referred to as an “LSI”).
2. Description of the Background Art
FIG. 23
shows a structure of a conventional LSI with a semiconductor test device (hereinafter referred to as a “LSI tester”) in the test state.
An LSI tester
500
is composed of a tester body
504
and a test head
506
. The tester body
504
includes a timing generator
501
generating a timing signal necessary as a condition of the LSI test, a waveform formatter
502
determining a waveform of rising or falling timing, and a power-supply/DC measuring unit
503
having a power supply for driving a device, a measuring portion for the DC of the device, and the like. The test head
506
makes direct transmissions of a signal to/from an LSI to be test
505
on the basis of a control signal obtained from the test body
504
through a cable
507
.
In testing the LSI to be test
505
, a pin electronic tester driver
509
stored in the test head
506
generates a test signal that is applied through a POGO pin
510
, a wire
512
of a DUT board
511
, an electrode
514
of a socket
513
, and a wire
516
of an LSI package
515
to the LSI to be test
505
. Conversely, after the operation of the LSI
505
, a reaction signal is transmitted along the same path to a tester comparator
517
in the LSI tester
500
, in which that signal is compared with an expected value EXP, by which the LSI tester
500
judges whether the LSI
505
operates as designed or not.
In testing the LSI
505
by the LSI tester
500
as described above, one of test items, the timing verification test, has caused a problem as described below. As the LSI
505
increases its operating speed, an interface thereof requires a clock speed of several hundreds MHz, which considerably reduces the value of setup or hold timing that is a product spec of the LSI
505
. This makes it difficult for the LSI tester
500
to perform a high-precision timing verification test with rigid timing conditions.
To give a concrete example, we refer to
FIGS. 24 and 25
that show a structure of a conventional I/O buffer cell
520
, and a timing relation between a data terminal
521
and a clock terminal
522
in the timing verification test, respectively.
As shown in
FIG. 24
, a clock CLK obtained from the clock terminal
522
is applied through a clock input portion
611
to respective control inputs of a driver
524
and a receiver
525
. The operation of the driver
524
and the receiver
525
is controlled by the clock CLK.
Further, data DATA obtained from the data terminal
521
is applied through a data input/output portion
612
to one input of the receiver
525
, and a reference voltage VREF is applied through a reference-voltage input portion
607
to the other input of the receiver
25
. The receiver
525
compares the data DATA and the reference voltage VREF, and according to the comparison result, outputs an internal signal obtained through buffering, via a signal output portion
610
to an internal logic
523
.
The output of the internal logic
523
is applied through a signal input portion
609
to an input of the driver
524
, the output of which is applied through the data input/output portion
612
to the data terminal
521
.
If a product standard of the setup time of the data DATA relative to the clock CLK
5
of the I/O buffer cell
520
provided in the LSI to be test
505
is 0.2 ns, for example, consider the case where the LSI tester
500
performs the timing verification test of whether the I/O buffer cell
520
in the LSI to be test
505
satisfies the timing condition that the setup time be 0.2 ns.
Even in the timing verification test with a setup time TS
1
in
FIG. 25
where L
1
depicts a waveform for the data DATA and L
3
a waveform for the clock CLK, the skew &agr; occurs in actual practice to both of the data DATA and the clock CLK. If the data DATA gains phase lead as depicted by a waveform L
2
and the clock CLK gains phase lag as depicted by a waveform L
4
, the timing verification test will be performed with a setup time ts
2
which is considerably longer than the original setup time TS
1
.
To be concrete, assuming that signal propagation time variations due to the timing skew of the signals caused by the LSI tester
500
are ±0.15 ns, those due to the lengths of the wire
512
of the DUT board
511
and the electrode
413
of the socket
513
are ±0.05 ns, and those due to the length of the wire
516
of the package
515
are ±0.1 ns, a phase difference between the clock CLK and the data DATA reaches 0.6 ns maximum.
Thus, when the clock CLK gains phase lag of 0.6 ns with respect to the data DATA, in order to surely ensure the setup time of 0.2 ns, a test program value tp is required to be set at −0.4 ns (so as to advance the clock CLK 0.4 ns faster than the data DATA). The reason for setting the value at −0.4 ns is as follows: If the test program value tp is set larger than −0.4 ns, when the clock CLK gains phase lag of 0.6 ns with respect to the data DATA, the timing verification test will be performed with the setup time of (tp+0.6) ns which is larger than 0.2 ns. This incurs the risk that the LSI to be test
505
may be wrongly judged as acceptable even if failing to satisfy the setup time of 0.2 ns.
The timing skew in the LSI tester
500
, however, still remains even though the test program value tp is set at −0.4 ns. Thus, when timing of the actual application of the signals to the LSI
505
is the worst (the data DATA gains a phase lag of 0.6 ns with respect to the clock CLK), the timing skew of −1.0 ns may occur.
When the timing of the application is the worst as described above, most of acceptable LSIs to be test
505
will be judged as defective, which causes extreme reduction in yield of the LSI
505
.
SUMMARY OF THE INVENTION
A first aspect of the present invention is directed to a semiconductor device comprising a first input/output buffer cell receiving first and second input signals and a first test-mode signal and buffering the first input signal to output an internal signal. The first input/output buffer cell comprises: delay means for receiving the first input signal and delaying the first input signal for a predetermined delay time to output a first delay input signal; first input-signal selecting means for outputting either of the first delay input signal and the second input signal as a first selection signal on the basis of the first test-mode signal; and internal-signal output means for buffering the first input signal to output the internal signal, the operation of the internal-signal output means controlled by the first selection signal.
Preferably, according to a second aspect of the present invention, the semiconductor device of the first aspect further comprises: a second input/output buffer cell for buffering the internal signal to output an output signal to the outside. The operation of the second input/output buffer cell is controlled by the second input signal.
Preferably, according to a third aspect of the present invention, the semiconductor device of the second aspect further comprises: an internal-signal processing circuit for processing the internal signal in a predetermined way to output a processed signal; and signal control means for receiving a second test-mode signal and controlling the validity or invalidity of outputting the processed signal to the first and the second input/output buffer cells on the basis of the second test-mode signal.
Preferably, according to a fourth aspect of the present invention, the semiconductor device of the first aspect further comprises: an internal-signal processing circuit for processing the internal signal in a predetermined way to output a processed signal; second input-signal selecting means for receiving a second test-mode signal and outputting either of the processed sign

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