Test bench interface generator for tester compatible simulations

Details Test bench interface generator for tester compatible simulations Test bench interface generator for tester compatible simulations

1997-06-17

1999-10-26

Teska, Kevin J.

G06F 9455

Patent

active

059742410

ABSTRACT:
A method for simulating an integrated circuit design that automatically generates an interface between a test bench and a device design for simulation. The method determines that the signal format and timing information of the test bench conforms to the constraints of some target ATE. If the information conforms, an array of buffers is created to provide the interface. Each of the buffers are defined according to the signal timing information. The interface is then incorporated into a test bench stimuli generator and the design is simulated. In this manner, the method allows for the generation of a simulation that can be then reproduced on any target ATE.

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patent: 5710934 (1998-01-01), Bona et al.
patent: 5812416 (1998-10-01), Gupte et al.

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