Test arrangement for testing semiconductor circuit chips

Details Test arrangement for testing semiconductor circuit chips Test arrangement for testing semiconductor circuit chips

2006-08-08

2006-08-08

Karlsen, Ernest (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C714S724000

Reexamination Certificate

active

07088122

ABSTRACT:
The invention relates to a test arrangement for testing semiconductor circuit chips, in which a test signal received via a primary test channel from a driver amplifier of an item of test equipment is distributed via parallel sub-channels to a plurality of inputs of one or more semiconductor circuit chips under test the test arrangement having signal buffering circuits arranged in each sub-channel that receive and buffer the test signal from the driver amplifier before feeding it to the inputs of the semiconductor circuit chip(s).

REFERENCES:
patent: 4780670 (1988-10-01), Cherry
patent: 5070297 (1991-12-01), Kwon et al.
patent: 6150831 (2000-11-01), Asai et al.
patent: 6360180 (2002-03-01), Breger
patent: 6452411 (2002-09-01), Miller et al.
patent: 6583639 (2003-06-01), Vogley
patent: 6591385 (2003-07-01), Krech et al.
patent: 6603324 (2003-08-01), Eldridge et al.

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