Test apparatus of integrated circuit

Details Test apparatus of integrated circuit Test apparatus of integrated circuit

2000-11-28

2002-10-01

Le, N. (Department: 2858)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S765010, C324S1540PB, C324S073100, C324S537000

Reexamination Certificate

active

06459290

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a test apparatus of an integrated circuit for checking operating conditions of plural integrated circuits having a self-diagnostic circuit.
2. Description of the Related Art
Recently, as a method for effectively testing a large-scaled and complicated semiconductor integrated circuit (hereinafter called “integrated circuit”), a burn-in test has been conducted. The burn-in test is a test for checking whether the integrated circuit operates normally under high-temperature environments or not, and is generally conducted in a constant temperature bath. In the burn-in test, an external test apparatus used in a normal test cannot be used, so that a self-diagnostic circuit is mounted in the integrated circuit itself and circuit operations is tested by this self-diagnostic circuit. In a configuration in which the self-diagnostic circuit is built into the integrated circuit, it is constructed so as to output a signal indicating a normal operation to a particular terminal in the case that an operation of the integrated circuit itself has correctly been performed.
A method for testing the integrated circuit will be described below. In self-diagnosis of the integrated circuit, the operating conditions of the integrated circuit can be checked by providing signals (power source application, GND fixing, clock input) necessary for operating the built-in self-diagnostic circuit and monitoring the obtained self-diagnostic results.
FIG. 7
shows a case of testing plural semiconductor integrated circuits on a silicon wafer. As shown in
FIG. 7
, plural semiconductor integrated circuits having a self-diagnostic circuit are arranged in a matrix shape on a silicon wafer
31
, and probes for respectively making connections to each the integrated circuit arranged on the silicon wafer
31
are arranged according to an array pattern of the integrated circuits on a connection probe wired sheet
30
. Further, on the connection probe wired sheet
30
, input control signal lines for semiconductor integrated circuit (hereinafter called “control signal lines”) are arranged in a row direction and output signal lines for self-diagnostic results (hereinafter called “output signal lines”) are arranged in a column direction. The control signal lines and the output signal lines, respectively, are connected to each the integrated circuit through the probes and as shown in the drawing, the control signal lines are connected in common with the plural integrated circuits arranged in the row direction and the output signal lines are individually connected to each the integrated circuit.
In the case of testing each the integrated circuit arranged on the silicon wafer
31
in the configuration described above, the connection probe wired sheet
30
and the silicon wafer
31
are overlaid and each the connection probes formed on the connection probe wired sheet
30
is connected to the corresponding integrated circuits formed on silicon wafer
31
, respectively. Then, the necessary signals such as a power source and a clock signal are respectively supplied to each the integrated circuit through the control signal lines, and the self-diagnostic circuit mounted in the integrated circuits is operated to test the own integrated circuit. The self-diagnostic result to each the integrated circuit is derived respectively through the output signal lines and the integrated circuits can be tested by monitoring this self-diagnostic result with an external monitor unit.
The conventional test method described above has the following problems. In the configuration, the output signal lines are derived individually from each the integrated circuit formed on the silicon wafer
1
and the integrated circuits are tested by individually monitoring the self-diagnostic results obtained through these output signal lines.
In the case of individually testing plural integrated circuits in a burn-in test carried out under high-temperature environments, it takes a considerable time to complete the tests of all the integrated circuits and the efficiency of the tests are reduced. Thus, the test time of the integrated circuits is preferably short. When the plural integrated circuits attempt to be tested at once in order to shorten the test time, output signal lines and monitor units by the number of integrated circuits are required in order to respectively monitor the self-diagnostic results obtained from each the integrated circuit in the configuration shown in FIG.
7
.
In the configuration shown in
FIG. 7
, the number of output signal lines arranged on the connection probe wired sheet
30
also increases in proportion to the number of integrated circuits formed on the silicon wafer
31
, but there is a physical limit to the number of output signal lines capable of being arranged on the connection probe wired sheet
30
. Also, it is impractical to prepare the monitor units by the number of integrated circuits. Further, with an increase in the output signal lines and the monitor units, the whole test system becomes complicated and expensive and this is reflected on manufacturing costs of the integrated circuits, so that a situation in which productivity of the integrated circuits including the test system reduces is caused.
SUMMARY OF THE INVENTION
The invention was made to solve the conventional problems, and it is an object of the invention to provide a test apparatus of a semiconductor integrated circuit capable of effectively monitoring each self-diagnostic result from plural integrated circuits and also reducing the number of output signal lines connected to the integrated circuits to a necessary minimum.
In order to solve the problems of the conventional art described above, a test apparatus of an integrated circuit according to the first aspect of the invention comprises plural integrated circuits in which a self-diagnostic circuit is included and a self-diagnostic result obtained from said self-diagnostic circuit is outputted and controlled by at least one control signal supplied from the outside, and each the self-diagnostic result of the plural integrated circuits is respectively supplied to one monitor every plural self-diagnostic results and control is performed by the control signal so that any one of the self-diagnostic results of the plural integrated circuits supplied to said monitor is outputted.
A test apparatus of an integrated circuit according to the second aspect of this invention is characterized in that the integrated circuits comprising an input terminal to which the control signal is supplied, an output terminal for outputting the self-diagnostic result and a tri-state buffer in which output disable or output enable of the self-diagnostic result is controlled by the control signal are arranged in a matrix shape, and while each the input terminal of the plural integrated circuits is connected in common every row through a control signal line for inputting the control signal, each the output terminal of the plural integrated circuits is connected in common every column through an output signal line for outputting the self-diagnostic result and is respectively connected to the monitor every column, and any one row of the plural integrated circuits is selected by the control signal and outputs of the self-diagnostic results of the selected integrated circuits are enabled and also outputs of the self-diagnostic results of the integrated circuits of the other rows are disabled, and the self-diagnostic results of each the integrated circuit arranged in the selected one row are respectively supplied to the monitor.
A test apparatus of an integrated circuit according to the third aspect of this invention is characterized in that the integrated circuits comprising plural input terminals to which a plurality of the control signals are respectively supplied, an output terminal for outputting the self-diagnostic result and a tri-state buffer in which output disable or output enable of the self-diagnostic result is controlled by a combination of the plural

Affiliated with

Also associated with

Rating

Test apparatus of integrated circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Test apparatus of integrated circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Test apparatus of integrated circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2947964