Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2001-08-06
2004-08-31
Cuneo, Kamand (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S757020, C324S754090
Reexamination Certificate
active
06784678
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a test apparatus for semiconductor circuits, in which the test apparatus has a specifically designed probe card that can be used to compensate for differences in height and planarity of test points in relation to contact surfaces of wafers. The probe card enables a subsequent feed movement of the test points in order to make simultaneous electrical contact with all of the contact surfaces.
After integrated circuits are fabricated, they are subjected to a first step of a functional test while they are still integrated in the wafer, that is to say before they are separated. This is done using a test apparatus that includes a wafer holder, known as a chuck, to hold a wafer, and also includes a test head. By being raised or lowered (Z position), the chuck can be moved towards the probe card that is configured above the chuck, and in addition, can be moved in the X and Y directions in order to be able to bring the contact surfaces of the various circuits that are located on the wafer into connection with the corresponding contact pins on the probe card. The test head usually includes test electronics for transmitting test signals and for evaluating the output signals coming from the individual integrated circuits on the wafer. The probe card carries the contacts and is connected to the test head via a holding mechanism. The probe card is usually a multilayer printed circuit board, known as the “performance board”, which is usually universal or has been designed specifically for the circuit to be tested. The probe card first, produces a connection with the tester electronics and second, via the contact pins, produces a connection to the wafer to be tested. It is usual for new printed circuit boards to be developed for each product to be tested, in order to take account of the respectively different association between a tester channel and the contact pins.
In order to carry out the actual test, the wafer that is located on the chuck is aligned, by means of electronically controlled stepping motors and image recognition technology, in such a way that the tips of the contact pins arrive as closely as possible to the center of the associated wafer contact area. The chuck is then moved upward with a predefined speed/travel profile, so that the springy tips of the contact pins finally produce electrical contact with the wafer contact areas (pads) with a defined contact pressure.
In the probe card technologies used hitherto, planarity differences in the probe card attitude, the wafer holder (chuck) and the wafer itself, caused by the devices, are compensated for by an appropriately springy construction of the contacts. The contact pins are normally produced from tungsten wire, are inserted manually into the probe card after appropriate shaping by bending, and are fixed with an epoxy resin. These contact pins have a certain flexibility, so that they are able to compensate for unevenness in the aforementioned components by mechanically springing with a corresponding overpressure. This leads to planarity differences manifesting themselves directly in different contact forces and scrub lengths and depths, as they are known, that is to say in the length and depth of the furrows scratched into the surface of the wafer contact areas by the contact pins.
This method, known from the prior art, hampers further miniaturization of the chip contact areas and the contact area layer thicknesses, since they can also lead to cracking—down as far as layers located under the contact areas. This becomes increasingly significant in the case of large-area contact configurations, for example, the simultaneous contact-making with up to 64 integrated circuits. Even slight angular displacements in this case produce large planarity differences.
A further example of contacts known from the prior art is the T2 probe card technology from the Formfactor company. This makes use of contact sets which are produced lithographically and are applied to a multilayer ceramic. The multilayer ceramic is used to supply the electrical contact between a performance board and the contacts. Because of the relatively high temperatures occurring during the sintering process, the connections are produced from tungsten, which entails the disadvantage of an increased contact resistance of about 5 ohms. Both the contacts and the ceramic substrate are spring-mounted, in order to compensate for planarity differences and to implement the movement of the contacts necessary to pierce the contact area oxide.
In order to compensate for the problems of the different levels of contact forces of the contacts, U.S. Pat. No. 5,803,983, for example, proposes a holding mechanism for the probe card, which can be tilted. While a pivot of the holding mechanism, which is circular in plan view, constitutes a tilting joint, two further points are provided at which the holding mechanism can be moved upward or downward with respect to the rest of the apparatus. The result of this is a tilting mechanism for the probe card. As a rule, the setting of the level of tilting is set once for an entire series of circuits on wafers to be tested with a probe card.
However, the mechanism proposed in U.S. Pat. No. 5,804,983 only permits tilting of the entire plane of the probe card in order to compensate for corresponding systemic tilting of the probe card, the probe card holder and the chuck, and systematic skewing of the wafers to be tested. The planarity differences within the probe card remain unconsidered in this case. In addition, in the mechanism proposed there, the action of making contact with the contact areas of the wafer, using the contacts of the probe card, is carried out by moving the chuck toward the probe card until the electrical connection is produced. The forces arising as a result of this coarse mechanism can still have the unwanted and disadvantageous secondary effects described above. In addition, compensating for unevenness on the wafers to be tested is not possible using the mechanism proposed there.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a test apparatus and a method of using the test apparatus which overcomes the above-mentioned disadvantageous of the prior art apparatus and methods of this general type. In particular, it is an object of the invention to provide a test apparatus with which it is possible to bring the contact areas of the integrated circuits to be tested into electrical contact with the test contacts as uniformly as possible, and therefore with relatively low requisite contact pressures.
With the foregoing and other objects in view there is provided, in accordance with the invention, a test apparatus for testing at least one semiconductor integrated circuit having a group of contact areas defining a wafer surface profile. The test apparatus includes a chuck for holding a wafer that has at least one semiconductor integrated circuit with a group of contact areas that define a wafer surface profile. The test apparatus also includes a test head that is configured opposite the chuck and that includes a performance board. The test apparatus also includes a probe card that is configured on the test head and that has contacts for making contact with the contact areas of the integrated circuit. The contacts have areas that are intended to come into contact with the contact areas of the integrated circuit and that define a test surface profile. The test apparatus also includes actuators that are configured on the probe card for aligning the test surface profile parallel with the wafer surface profile. The actuators are also for changing a distance between the performance board and the contacts in a direction substantially orthogonal to the wafer surface profile.
The invention relates to a test apparatus that has combined compensation for tilting and planarity and also a contact-making advance mechanism.
The invention also relates to an apparatus that, on the basis of low contact pressures and slight lateral contactin
Cuneo Kamand
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
Patel Paresh
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