Test apparatus for PCM/FDM transmultiplexer

Multiplex communications – Wide area network – Packet switching

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375 10, 371 27, 370 50, H04J 116, H04J 400, H04B 346, G01R 3128

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045983984

ABSTRACT:
A device is described which utilizes an addressing circuit to output, from a memory device, stored digital samples of an analog sinusoid, in logarithmic form, to a level control circuit, which modifies the digital level by means of adding a logarithmic scaler, and subsequently is encoded into a standard format, either linear, North American u-255 Law, or CCITT A-Law, and, after multiplexing with the respective bit rate. The addressing circuit has the capability to give an output with apparent frequencies in integer multiples of 8000/3989 Hz. Unused channels may be filled by a variety of digital signals, through use of a programmable memory device. Signalling control for the channels under interest is separate from the unused channels to aid in impulse noise testing. The signalling option can also be disabled.
A device which demultiplexes digital samples from a time division multiplex frame, encoded in linear, u-255 Law North American, or CCITT A-Law format, decodes the samples into 16 bit linear form via a memory device, and reconstructs the waveform into analog form via a digital to analog converter. The appropriate signalling information is also demultiplexed. Programmable gain is available digitally at the 16 bit linear decoding stage by utilizing a separate "page" of the memory device (up to 60.2 DB of gain).

REFERENCES:
patent: 4451918 (1984-05-01), Gillette
patent: 4486876 (1984-12-01), Gaunt, Jr. et al.
patent: 4510598 (1985-04-01), Gockler et al.

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