Test apparatus and test method for testing a device under test

Data processing: measuring – calibrating – or testing – Testing system – For transfer function determination

Reexamination Certificate

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Details

C702S120000

Reexamination Certificate

active

11056330

ABSTRACT:
A testing apparatus for testing a device under test (DUT) includes a performance board; a main frame for generating a test signal for testing the DUT and determining pass/fail of the DUT based on an output signal output by the DUT; a pin electronics between the main frame and the performance board and performs sending and receiving signals between the main frame and the DUT; a deterministic jitter injecting unit for receiving the output signal without passing through the pin electronics and inputting a loop signal, which is the received output signal into which a deterministic jitter is injected, to an input pin of the DUT without passing through the pin electronics; and a switching unit for determining whether the input pin of the DUT is provided with the test signal output by the pin electronics or the loop signal output by the deterministic jitter injecting unit.

REFERENCES:
patent: 6100815 (2000-08-01), Pailthorp
patent: 6173427 (2001-01-01), Tsukagoshi
patent: 6961745 (2005-11-01), Laquai et al.
patent: 7010444 (2006-03-01), Nishikobara et al.
patent: 2002/0174159 (2002-11-01), Laquai
patent: 2003/0156545 (2003-08-01), Shimanouchi et al.
patent: 2005/0031029 (2005-02-01), Yamaguchi et al.
patent: 2005/0172181 (2005-08-01), Huliehel
patent: 1464970 (2004-10-01), None
patent: WO-03/071297 (2003-08-01), None
Laquai, Bernd, Cai, Yi, “Testing Gigabit Multilane SerDes Interfaces with Passive Jitter Injection Filters,” Oct. 30-Nov. 1, 2001, Test Conference, 2001, Proceedings, International, pp. 297-304.
“New Paradigm for Signal Paths in ATE Electronics are Needed for Serialcom Device Testing,” ITC International Test Conference, pp. 903 to 912, by Masashi Shimanouchi (referred to in the specification, paragraph [0003]), 10 pages.

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