Test apparatus and test method

Details Test apparatus and test method Test apparatus and test method

2006-04-04

2006-04-04

Nguyen, Vinh (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S1540PB

Reexamination Certificate

active

07023233

ABSTRACT:
A test apparatus for testing switching speed of a circuit, which includes a pre-stage logic element outputting a first or second level voltage and a post-stage logic element to which the output signal of the pre-stage logic element is input, is provided, wherein the post-stage logic element includes the post-stage FET, a gate terminal of which the output signal is input to, for outputting a different level of voltage according to the case that the output signal voltage is higher or lower than a predetermined threshold voltage, and the test apparatus includes a threshold voltage setting unit for setting a threshold voltage of a post-stage field effect transistor (FET) to be different from that in a normal operation by setting a substrate voltage of the post-stage FET to have a value different from that in the normal operation of the circuit; a delay time measuring unit for measuring a delay time of the circuit to which the threshold voltage different from that in the normal operation is set; and an error detecting unit for detecting an error in switching speed of the circuit based on the delay time.

REFERENCES:
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Hurst, et al.; “Flip-Flop Sharing in Standard Scan Path to Enhance Delay Fault Testing of Sequential Circuits”; Center for Digital Systems Engineering. Research Triangle Institute; 1995 IEEE; pp. 346-352.
Hatayama, et al.; “Application of a Design for Delay Testability Approach to High Speed Logic LSIs”; Hitachi Information Technology Co., Ltd.; 1997 IEEE; pp. 112-115.
Touba, et al.; “Applying Two-Pattern Tests Using Scan-Mapping”; Center for Reliable Computing, Stanford University; 1996 IEEE; pp. 393-397.
MacDonald, et al.; “Delay Testing of SOI Circuits: Challenges with the History Effect”; ITC International Test Conference; 1999 IEEE; pp. 269-275.
Mizuno; “Leakage Current and Its Suppression Technique in Low-Voltage High-Speed CMOS LSIs”; vol. J83-C, No. 10, Oct. 2000; pp. 926-935.

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