Test apparatus and method for testing digital system

Electricity: measuring and testing – Measuring – testing – or sensing electricity – per se – With rotor

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371 223, G01R 3128

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active

051987597

ABSTRACT:
A testing apparatus and method for testing of assemblies (BG1, BG2 . . . , BGn) in digital electronic systems, which permits a test on a system level without a fixed pre-setting of the number and position of the assemblies to be tested. On each assembly, control circuits are used for testing additional control circuits embodied as interfaces comprising two control units, one of which is assigned to a system scan bus, and the other of which is assigned to an assembly scan bus. The two control units can mutually exchange the active control function so that one unit is active at a given time. In this way it is possible to address a control unit of an assembly via the system scan bus without affecting the assembly scan bus which is connected with the deactivated other control unit. This arrangement first permits the individual assemblies to be selected by means of their slot position address and only thereafter to test them in a test operation. Neither the wiring of the system scan bus nor the test software need be changed if assemblies are removed or their positions are changed.

REFERENCES:
patent: 4038648 (1977-07-01), Chesley
patent: 4701921 (1987-10-01), Powell et al.
patent: 4875003 (1989-10-01), Burke
patent: 4947357 (1990-08-01), Stewart et al.
patent: 4963824 (1990-10-01), Hsieh et al.
Lee Whetsel, "A Proposed Standard Test Bus and Boundary Scan Architecture", Nov. 1988, pp. 1-5, Wescon 88/Conference Record.
IBM Technical Disclosure Bulletin, vol. 32, No. 4A, "Using a Portion of the Boundary Register as the Identification Register", Sep. 1989, pp. 262-264.
IEEE Standard 1149.1-1990, The Institute of Electrical and Electronics Engineers, Inc., New York, N.Y., USA, for Test Access Ports (TAP) and Boundary-Scan Architecture, 10 pages, approved Feb. 15, 1990, IEEE Standards Board.

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