Test apparatus and method for a computer parallel port

Details Test apparatus and method for a computer parallel port Test apparatus and method for a computer parallel port

1994-04-28

1996-09-17

Beausoliel, Jr., Robert W.

Excavating

371 681, 371 205, G06F 1134

Patent

active

055577415

ABSTRACT:
A test apparatus and method for testing a port of a computer system. The port has a plurality of output lines and a single input line. The apparatus includes: (1) a receiver circuit for receiving a datum transmitted in parallel from the computer system via the plurality of output lines, (2) a storage circuit, coupled to the receiver circuit, for temporarily storing the datum from the output lines and (3) a transmitter circuit, coupled to the storage circuit, for serially transmitting the datum via the input line to the computer system. The computer system compares the datum transmitted from the computer system to the datum received by the computer system to verify a proper functioning of the output lines and input line.

REFERENCES:
patent: 4563762 (1986-01-01), Sibley
patent: 5166923 (1992-11-01), Ohmori et al.
patent: 5247690 (1993-09-01), Fain
patent: 5357519 (1994-10-01), Martin et al.

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