Ternary CAM cell with DRAM mask circuit

Details Ternary CAM cell with DRAM mask circuit Ternary CAM cell with DRAM mask circuit

2001-02-08

2002-06-04

Ho, Hoai V. (Department: 2818)

Static information storage and retrieval

Associative memories

Ferroelectric cell

C365S168000

Reexamination Certificate

active

06400593

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to content addressable memory (CAM) arrays. More specifically, the present invention relates to CAM arrays including ternary CAM cells.
DISCUSSION OF RELATED ART
Semiconductor memory devices fall into two broad categories: read only memory (ROM) devices, and read-write or “random access” memory (RAM) devices. ROM (e.g., EPROM or EEPROM) devices are non-volatile devices primarily used to store data when system power is turned off. In contrast, RAM devices temporarily store data that is used during system operation. RAM devices are typically volatile in that the data stored in a RAM device is lost when power is turned off. RAM devices are roughly divided into two types: static random access memory (SRAM) devices, and dynamic random access memory (DRAM) devices.
An SRAM device consists of a basic bistable flipflop circuit that needs only an applied DC current to retain a data value. To store a logic “1” data value (bit), the bistable flipflop is biased into a first stable state, and to store a logic “0” data value, the bistable flipflop is biased into its second stable state. The bistable flipflop maintains the first or second stable state until an opposite biasing voltage is applied that “flips” the bistable flipflop from the first to the second (or the second to the first) stable state. While the stable data storage of SPAM devices provides certain advantages, a main disadvantage of SRAM devices is their relatively large size due to the multiple (typically six or more) transistors required to form and access the bistable flipflop circuit.
In contrast to SRAM devices, DRAM devices stores a data value as a charge on a capacitor or wire (referred to herein as a “storage node”). The main advantage of DRAM devices is that a basic DRAM memory cell requires only a single transistor and a capacitor (or wire), thereby making DRAM cells significantly smaller and less expensive to produce than SRAM cells. The main disadvantage of DRAM devices is that the data values stored in the storage node decay over time, thereby requiring refresh circuitry that periodically reads and rewrites (refreshes) the stored data values to prevent their loss. Due to the sensitivity typical of DRAM devices, this refresh operation must be performed independent of other (e.g., read or write) operations. In particular, the data value (voltage) stored in the storage node of a DRAM memory cell is read using a sense amplifier during a read phase of the refresh operation, and then the sense amplifier refreshes (rewrites) the sensed data value during a write phase of the refresh operation. Due to the read phase of the refresh operation, the number of memory cells in each column of a DRAM array must be minimized. That is, the length (i.e., capacitance) of bit lines increases with the number of DRAM memory cells arranged in a column that are connected to these lines. Because the data values are partially decayed before being transmitted from each DRAM memory cell onto bit lines, this capacitance can generate read phase errors if the bit lines are too long. In particular, this sensitivity restricts the use of DRAM devices in the direct control a logic gate or the gate terminal of a pass transistor in an integrated circuit.
Conventional RAM arrays include RAM cells arranged in rows and columns, and addressing circuitry that accesses a selected row of RAM cells using address data corresponding to the physical address of the RAM cells. That is, data words stored in the rows of conventional RAM cells are accessed by applying address signals to the RAM array input terminals. In response to each unique set of address signals, a RAM array outputs a data word that is read from a group of RAM cells designated by the address.
Unlike conventional RAM arrays, content addressable memory (CAM) arrays include CAM cells that are addressed in response to their content, rather than by a physical address within a RAM array. Specifically, a CAM array receives a data word that is compared with all of the data values stored in the CAM cells located in each row of the CAM array. In response to each unique data word applied to the CAM array input terminals, the rows of CAM cells within the CAM array assert or de-assert associated match signals indicating whether or not all of the data values stored in the CAM cells of a row match the applied data word. CAM arrays are useful in many applications, such as search engines.
Similar to conventional RAM devices, CAM cells can either be formed as DRAM devices, in which data values are stored in storage nodes formed by capacitors or wires, or SRAM devices, in which data values are stored using bistable flipflop circuits. Similar to conventional RAM cells, DRAM CAM cells provide an advantage in that they are typically smaller than SRAM CAM cells, but require a refresh operation that can impede high speed match operations. In addition, DRAM CAM arrays are typically limited in size due to the capacitance problems, discussed above, that are associated with DRAM memory cells. In contrast, SRAM memory cells typically require more transistors (and, hence, more substrate area) than DRAM cells, but avoid the capacitance problems associated with DRAM CAM cells.
CAM cells are typically defined by the number of data values that they store. For example, binary CAM cells stores one of two logic values: a logic high value or a logic low value. Ternary CAM cells store one of three logic values: a logic high value, a logic low value, and a “don't care” logic value. A “don't care” logic value is a logic value that produces a match condition for any applied compare data value. When the logic value stored in a ternary CAM cell matches an applied data value, assuming all other CAM cells coupled to the CAM array row also match, then the voltage on the match line coupled to the ternary CAM cell is maintained at the match value (e.g., a logic high value), thereby indicating that a match has occurred. In contrast, when the logic value stored in the ternary CAM cell does not match an applied data value, then the voltage on the match line coupled to the ternary CAM cell is changed to the no match value (e.g., pulled down to a logic low value), thereby indicating that a match has not occurred. A ternary CAM cell storing a “don't care” value will provide a match condition for any data value applied to that CAM cell. This “don't care” capability allows CAM arrays to indicate when a data value matches a selected group of ternary CAM cells in a row of the CAM array.
Higher order CAM cells store additional data values. For example, a four state (“quad” CAM cell stores a logic high value, a logic low value, a logic high “don't care” value, and a logic low “don't care” value. Thus, a CAM cell storing four states beneficially stores a data value (e.g., a high or low value) and simultaneously indicates whether that data value is to be involved in a match operation (e.g., a logic high or a logic high “don't care”). As a result, a read operation on a four-state CAM cell storing a “don't care” value distinguishes the “don't care” value read from the CAM cell as either a logic high “don't care” value or a logic low “don't care” value. Match operations performed by a four-state CAM cell are similar to the ternary CAM cell described above.
FIG. 10
is a schematic diagram of a conventional ternary CAM cell
1000
. CAM cell
1000
is a sixteen-transistor (
16
-T) device including two 6-transistor (
6
-T) SRAM cells
1001
A and
1001
B and a 4-T exclusive-NOR (comparator) circuit
1001
C. SRAM cell
1001
A includes n-channel transistors
1010
,
1011
,
1014
, and
1015
and p-channel transistors
1022
and
1023
. Transistors
1014
,
1015
,
1022
, and
1023
are cross-coupled to form a storage latch having storage node N
1
and inverted storage node N
1
#. Access transistors
1010
and
1011
couple storage node N
1
# and N
1
, respectively, to inverted bit line B
1
# and bit line B
1
, respectively. Similarly, SRAM cell
1001

Affiliated with

Also associated with

Rating

Ternary CAM cell with DRAM mask circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Ternary CAM cell with DRAM mask circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Ternary CAM cell with DRAM mask circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2903283