Ternary CAM array

Details Ternary CAM array Ternary CAM array

2000-05-18

2001-07-17

Elms, Richard (Department: 2824)

Static information storage and retrieval

Associative memories

Ferroelectric cell

C365S189070

Reexamination Certificate

active

06262907

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to content addressable memory (CAM) arrays. More specifically, the present invention relates to ternary CAM cells and methods for operating these cells in a CAM array.
DISCUSSION OF RELATED ART
Unlike conventional random access memory (RAM) arrays, CAM arrays include memory cells that are addressed in response to their content, rather than by a physical address within a RAM array. That is, data words stored in a RAM array are accessed by applying address signals to the RAM array input terminals. In response to each unique set of address signals, a RAM array outputs a data value that is read from a portion of the RAM array designated by the address. In contrast, a CAM array receives a data value that is compared with all of the data values stored in rows of the CAM array. In response to each unique data value applied to the CAM array input terminals, the rows of CAM cells within the CAM array assert or de-assert associated match signals indicating whether or not one or more data values stored in the CAM cell rows match the applied data value.
CAM arrays are useful in many applications, such as search engines. For example, assume an employee list is searched to identify all employees with the first name “John”. The first names are written into a CAM array such that they are stored in a predetermined order (e.g., according to employee number). The input data value (“John”) is then applied to the CAM input terminals. When one or more stored data values match the input data value, the match line coupled to the one or more matching rows of CAM cells generates a high output signal. By identifying which rows have associated high match lines, and comparing those row numbers with the employee number list, all employees named “John” are identified. In contrast, to search a RAM array containing the same employee list, a series of addresses must be applied to the RAM array so that each stored data value is read out and compared with the “John” data value. Because each RAM read operation takes one clock cycle, a relatively large amount of time is required to read and compare a particular data value with all data values stored in a RAM array.
There are two types of CAM cells typically used in CAM arrays: binary CAM cells and ternary CAM cells. Binary CAM cells store one of two bit values: a logic high value or a logic low value. When the logic value stored in the binary CAM cell matches an applied data value, then the match line coupled to the binary CAM cell is maintained at a logic high value (assuming all other CAM cells coupled to the CAM array row also match), thereby indicating that a match has occurred. In contrast, when the logic value stored in the binary CAM cell does not match an applied data value, then the match line coupled to the binary CAM cell is pulled down, thereby indicating that a match has not occurred. Ternary CAM cells can store any one of three values: a logic high, a logic low, or a “don't care” value. When storing logic high and logic low values, a ternary CAM cell operates like a binary CAM cell. In addition, a ternary CAM cell storing a don't care value will provide a match condition for any data bit value applied to that CAM cell. This “don't care” capability allows CAM arrays to indicate when a data value matches a selected group of ternary CAM cells in a row of the CAM array. For example, assume each row of a ternary CAM array has eight ternary CAM cells. Additionally assume that the first four ternary CAM cells of each row each store one of a logic high and a logic low value (for comparison to the first four bits of an input 8-bit data value) and the last four ternary CAM cells of each row store “don't care” values. Under these conditions, when an 8-bit data value is applied to the ternary CAM array, a match occurs for each row of the CAM array in which the data values stored in the first four ternary CAM cells match the first four bits of the applied 8-bit data value.
Binary and ternary CAM cells can be characterized as volatile (i.e., in which the logic high, logic low, or don't care value is stored in volatile components, such as capacitors), or non-volatile (i.e., in which values are stored in non-volatile components, such as EPROM transistors).
FIG. 1
is a schematic diagram of a first prior art volatile ternary CAM cell
100
as described in U.S. Pat. No. 5,642,320. CAM cell
100
includes volatile (e.g., field-effect) transistors Q
1
-Q
6
. Transistor Q
1
has a drain coupled to the source of transistor Q
2
. Transistor Q
3
has a drain coupled to the source of transistor Q
4
. Transistor Q
2
has a gate coupled to the drain of transistor Q
6
. Transistor Q
4
has a gate coupled to the drain of transistor Q
5
. A match line is commonly coupled to the sources of transistors Q
1
and Q
3
. A bit line BL is commonly coupled to the gate of transistor Q
1
and the source of transistor Q
5
. An inverted bit line BL# is commonly coupled to the gate of transistor Q
3
and the source of transistor Q
6
. A word line WL is commonly coupled to the gates of transistors Q
5
-Q
6
. The drains of transistors Q
2
and Q
4
are commonly coupled to ground. CAM cell
100
stores one of a logic high, a logic low, and a don't care value in dynamic storage nodes N
A
and N
B
. A don't care value is a value that results in a match condition for all applied data values. To store a logic high value, a logic high value is applied to bit line BL and a logic low value applied to inverted bit line BL#. A logic high value is applied to word line WL to turn on transistors Q
5
-Q
6
, thereby coupling the logic high value of the bit line BL to both node N
B
and the gate of transistor Q
4
and coupling the logic low value of the inverted bit line BL# to both node N
A
and the gate of transistor Q
2
. As a result, node N
A
stores a logic low value and node N
B
stores a logic high value.
To store a logic low value, a logic low value is applied to bit line BL and a logic high value applied to inverted bit line BL#. A logic high value is applied word line WL to turn on transistors Q
5
-Q
6
, thereby coupling the logic low value of the bit line BL to both node N
B
and the gate of transistor Q
4
and coupling the logic high value of the inverted bit line BL# to both node N
A
and the gate of transistor Q
2
. As a result, node N
A
stores a logic high value and node N
B
stores a logic low value.
To store a don't care value, a logic low value is applied to both bit line BL and to inverted bit line BL#. A logic high value is applied word line WL to turn on transistors Q
5
-Q
6
, thereby coupling the logic low value of the bit line BL to both node N
B
and the gate of transistor Q
4
and coupling the logic low value of the inverted bit line BL# to both node N
A
and the gate of transistor Q
2
. As a result, both nodes N
A
and node N
B
store logic low values.
CAM cell
100
performs a compare operation by pre-charging the match line ML to a logic high value and then sensing any current on the match line ML. A no-match condition during a compare operation results in the discharge of the match line ML to ground. The discharge causes a current to flow between match line ML and ground. A current sensor coupled to match line ML senses this current flow, thereby indicating the no-match condition. In contrast, a match condition during a compare operation results in the match line ML remaining charged to a logic high value. Because the match line ML is not discharged during a match condition, no current will flow on match line ML. As a result, no current is sensed on match line ML by the associated current sensor, thereby indicating the match condition.
During a compare operation, word line WL is held to a logic low value and the compare data is applied to bit line BL (e.g., logic high value) and inverted bit line BL# (e.g., logic low value). If CAM cell
100
stores a logic high value, then the logic low value stored at node N
A
turns off transistor Q
2
, thereby de-coupli

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