Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – With particular signal path connections
Reexamination Certificate
2002-09-19
2004-11-30
Wilson, Allan R. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
With particular signal path connections
C257S203000, C257S204000
Reexamination Certificate
active
06825510
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to semiconductor devices and, more particularly, to semiconductor power devices and methods for fabricating such devices.
BACKGROUND OF THE INVENTION
Power switching devices of the type which operate on field effect principles are devices of choice for handling large currents and large voltages. These devices provide low on-resistance, fast switching speeds and low current draw during switching operations. Typically, such devices are formed on a semiconductor layer with a number of transistor cells connected in parallel to maximize current handling capability. For a conventional diffused MOS (DMOS) transistor, each cell includes a doped source region, a body region and a channel region controllable with a gate electrode. Commonly, such devices are formed with a trenched gate electrode to increase device density. Another common power device for handling high currence is the Insulated Gate Bipolar Transistor (IGBT) which is a four layer device that operates on field effect principles.
Generally, the operating voltage of such devices is dependent in part on the sustainable voltage that the device will provide during the off conduction state, in particular, during reverse bias conditions. It is conventional in power device design to incorporate edge termination techniques along the outer periphery of the device on which the transistors are formed in order to increase the voltage at which junction breakdown would occur. Specifically, the breakdown voltage must be significantly higher than that of the region in which active transistor cells operate.
Numerous techniques are known for maximizing the breakdown voltage in the termination region. These include field rings, channel stop implants and field plates. Absent such techniques it would not be possible to approach the theoretical breakdown voltage of a semi-infinite junction. For further discussion on edge termination design see Ghandhi,
Semiconductor Power Devices
, John Wiley & Sons, Inc., 1977 (ISBN 0-471-02999-8), incorporated herein by reference, which discusses this subject at chapter two. See, also, Baliga,
Modern Power Devices
, PWS Publishing Company, Boston, Mass., 1996 (ISBN 0-534-94098-6), also incorporated herein by reference, which provides relevant discussion at chapter three. In addition to conventional field rings and field plates, trenched field plates have been considered for edge termination applications. U.S. Pat. No. 5,233,215 discloses use of one or more trenched, floating field plates in combination with field rings in order to terminate a silicon carbide MOSFET. U.S. Pat. No. 5,578,851 discloses field rings separated by trenches, allowing the field rings to be closely spaced in order to conserve area. The trenches may be filled with polysilicon electrically connected to the MOSFET gate electrode.
As performance requirements continue to become more stringent, it is desirable to develop additional techniques to elevate the breakdown voltage in the termination region of a power device.
SUMMARY OF THE INVENTION
According to the invention, an insulator layer may be positioned with respect to a diffusion region in a layer of opposite conductivity type, to contain, when a reverse bias voltage is applied across the junction, the peak field concentration within the insulator layer. In one exemplary embodiment of the invention, a semiconductor device is provided having a first layer of first conductivity type with a diffusion region of second conductivity type formed along the surface and extending to a first depth within the first layer, the diffusion region forming a pn junction with the first layer. A field plate has a first portion extending over the diffusion region and a second portion extending to a peripheral region of the device and a dielectric layer is formed within the first layer, extending to at least the first depth. Preferably, the dielectric layer is positioned between the diffusion region and the peripheral region in abutment with the diffusion region. The dielectric layer may be formed in a trench extending into the diffusion region beyond the first depth.
In other embodiments a semiconductor device with a field plate structure formed along an outer periphery includes a semiconductor layer of predominately a first net conductivity type and a diffusion region of a second net conductivity type formed in the semiconductor layer. An insulator layer is formed in contact with the diffusion region and extends into the semiconductor layer to at least the same depth as the diffusion region. A field plate extends from over the diffusion region to over the insulator layer.
A method is provided for altering the peak field concentration under reverse bias conditions in a semiconductor device of the type having a first layer of first conductivity type forming a junction with a diffusion region of second conductivity type formed along an upper surface. A field plate is formed over the surface with a first portion extending over the diffusion region and a second portion extending peripherally to position the peak field concentration in a region of the first layer other than the junction. In one example, an insulative layer is formed in the first layer in abutment with the diffusion region to position the peak field concentration within the insulative layer. An edge termination ring may be formed along the upper surface, extending from the insulative layer to the outer periphery of the device.
A method is also provided for controlling reverse bias breakdown voltage characteristics in a semiconductor device layer having an insulator region formed next to a diffusion region. The method includes locating the peak field concentration, which occurs in the device layer during reverse bias conditions, in the insulator region. In one embodiment, the peak field concentration is located by positioning a field plate over the insulator region and the diffusion region. Preferably, the insulator region is formed through the diffusion region.
A method for controlling avalanche breakdown conditions applies to a semiconductor layer of a first conductivity type and a region of a second conductivity type formed in the layer. A field plate is positioned over the region of second conductivity type and an insulator is positioned within the layer to place the peak field concentration during the reverse bias condition entirely within the insulator. The insulator may extend into the semiconductor layer to a depth greater than the depth of the region of the second conductivity type.
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Fairchild Semiconductor Corporation
FitzGerald Thomas R.
Wilson Allan R.
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