Television – Receiver circuitry – Power supply
Reexamination Certificate
2000-05-15
2003-02-04
Kostak, Victor R. (Department: 2614)
Television
Receiver circuitry
Power supply
C345S212000
Reexamination Certificate
active
06515716
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an image display device capable of saving power.
2. Description of the Related Art
As for image display devices (monitors) (display devices) to be used while connected to computer systems, image display devices capable of automatically saving power to reduce power consumption have been put on the market. For example, in the U.S.A, the Video Electronics Standards Association has stipulated the standards on power saving for saving power to be consumed by display devices for computer systems. The standards specify an on mode, a standby mode, a suspension mode, and an active-off mode. The on mode is a mode in which an image is displayed. The standby mode, suspension mode, and active-off mode are modes in which no image is displayed, ranging in sequential order from what is least effective at power saving to what is most effective at power saving. The power saving modes are switched according to if horizontal and vertical sync signals have been sent from a computer system.
On mode: when both horizontal and vertical sync signals are transmitted, an image is displayed on the surface of a cathode-ray tube.
Standby mode: when the vertical sync signal is transmitted but the horizontal sync signal is not transmitted, power is saved to the least extent.
Suspension mode: when the horizontal sync signal is transmitted but the vertical sync signal is not transmitted, power is saved to the moderate extent.
Active-off mode: when both the horizontal and vertical sync signals are not transmitted, power is saved to the greatest extent.
Referring to
FIG. 7
, an image display device capable of saving power in accordance with a related art will be described below. TR, TG, TB, TH, and TV denote input terminals through which a red signal R, a green signal G, a blue signal B, a horizontal sync signal H, and a vertical sync signal V are sent from a computer system serving as a video signal source.
The red, green, and blue signals R, G, and B received through the input terminals TR, TG, and TB and the horizontal and vertical sync signals H and V received through the input terminals TH and TV are transferred to a video circuit
1
. The video circuit
1
processes the red, green, and blue signals R, G, and B. The red, green, and blue signals R, G, and B sent from the video circuit
1
are transferred to a cathode-ray tube drive circuit
2
, and then amplified. Thereafter, the signals are transferred to cathodes of an electron gun associated with each of the color signals in the cathode-ray tube
3
. The video circuit
1
and drive circuit
2
are generically called a signal processing circuit.
A digital amplification factor control signal sent from a CPU
5
that will be described later is transferred to a D/A converter
6
and converted into an analog amplification factor control signal. The analog amplification factor control signal is transferred to the drive circuit
2
, whereby an amplification factor is controlled.
The central processing unit (CPU)
5
serving as a sync signal sensor senses if horizontal and vertical sync signals H and V have been received through the input terminals TH and TV. Moreover, the CPU
5
produces horizontal data and vertical data, transfers the data to a horizontal drive signal generation circuit
8
and a vertical sawtooth signal generation circuit
7
respectively. The horizontal drive circuit
8
and vertical sawtooth signal generation circuit
7
generate a horizontal driving signal (horizontal pulsating signal) and a vertical sawtooth signal respectively. The horizontal driving signal (horizontal pulsating signal) and vertical sawtooth signal are transferred to a horizontal/vertical deflection circuit
9
. Horizontal and vertical deflection signals sent from the horizontal/vertical deflection circuit
9
are transferred to a horizontal/vertical deflection yoke
4
of the cathode-ray tube
3
. The horizontal driving signal generated by the horizontal driving signal generation circuit
8
is transferred to a high-voltage circuit (high-voltage generation circuit)
10
. A resultant high voltage is applied to an anode of the cathode-ray tube
3
.
Reference numeral
15
denotes a power source device composed of a chopper switching regulator
16
and a transformer
17
. The chopper switching regulator
16
is connected to an outlet of an AC power source (not shown) through an AC voltage input terminal (plug) TAC. The chopper switching regulator
16
commutates and smoothes a commercial AC voltage, and thus converts it into a DC voltage. Application and non-application of the DC voltage are switched using a switching means, whereby a pulsating voltage is produced and applied to a transformer
17
. The duty factor of the pulsating voltage is varied by a load current. A main power source
18
, a heater power source
19
, and a CPU power source
14
are connected to the transformer
17
.
In the main power source
18
, a transformer receives a pulsating voltage from the transformer
17
. A pulsating voltage of a different level is then produced. Thus-produced pulsating voltages are commutated and smoothed in order to produce DC voltages of 5 V, 12 V, 80 V, and 200 V. The voltage of 5V is applied to the horizontal driving signal generation circuit
8
. The voltages of 80 V and 200 V are applied to the drive circuit
2
. The voltage of 200 V is applied to the horizontal/vertical deflection circuit
9
and high-voltage circuit
10
. The voltage of 12 V is applied to another circuit that is not shown. In the heater power source device
19
, a step-down transformer receives the pulsating voltage from the transformer
17
. The low pulsating voltage is commutated and smoothed in order to produce a voltage of 6.3 V. The voltage of 6.3 V is applied to a heater HT of the cathode-ray tube
3
A manual switch of the main power source
18
will be described below. The manual switch is connected in series with a power terminal of the main power source
18
, at which a DC voltage of, for example, 12 V is developed, and a circuit, to which the DC voltage of 12 V is applied, and inserted between the power terminal and circuit. When the manual switch is turned off, a load current flowing into the chopper switching regulator
16
decreases greatly. This causes the duty factor of the pulsating voltage sent from the regulator
16
to become 0. Consequently, no voltage pulse is produced by the transformer
17
. When the manual switch is turned on, the load current flowing into the chopper switching regulator
16
assumes a normal value. The duty factor of the pulsating voltage applied from the regulator
16
assumes a normal value. Consequently, the transformer
17
produces a voltage pulse.
In the CPU power source
14
, a step-down transformer receives a pulsating voltage from the transformer
17
. The low pulsating voltage is commutated and smoothed, whereby a voltage of 5 V is produced. The voltage of 5 V is applied to the CPU
5
.
The CPU
5
controls an on-to-off transition to be made by the main power source
18
and heater power source
19
according to if the horizontal and vertical sync signals have been received through the input terminals TH and TV respectively. Moreover, the CPU
5
controls an amplification factor to be exhibited by the drive circuit
2
. When both the horizontal and vertical sync signals H and V have been sent to the CPU
5
, the CPU
5
turns on the main power source
18
and heater power source
19
(on mode). At this time, an image is displayed on the surface of the cathode-ray tube
3
. In the power saving modes described below, no image is displayed on the surface of the cathode-ray tube
3
. When the horizontal sync signal H has not been sent to the CPU
5
but the vertical sync signal V has been sent thereto, the CPU
5
turns on the main power source
18
and heater power source
19
. Moreover, the CPU
5
minimizes the amplification factor to be exhibited by the drive circuit
2
(first-step power saving: standby mode). When the vertical sync signal V has not been sent to th
Nomura Tetsuya
Suzuki Satoru
Kostak Victor R.
Maioli Jay H.
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