Terminal adapter capable of reducing a memory capacity of a buff

Details Terminal adapter capable of reducing a memory capacity of a buff Terminal adapter capable of reducing a memory capacity of a buff

1994-09-08

1997-07-08

Chin, Stephen

Pulse or digital communications

Bandwidth reduction or expansion

Television or motion video signal

375249, 375377, 348384, H04B 166, H04B 1406, H04L 2300

Patent

active

056469594

ABSTRACT:
In a terminal adapter which is located between a data terminal equipment unit (11) and a data communication network (12) and which includes a buffer memory (22, 27) for memorizing an original data signal sequence sent from each of the data terminal equipment unit and the data communication network, the original data signal sequence is subjected to data compression by a data compression circuit to be thereafter memorized into the buffer memory and to be read out of the buffer memory as a readout data signal sequence. The readout data signal sequence is expanded by a data expansion circuit (32, 35) to be sent to the data terminal equipment unit or the data communication network at a transmission rate matched therewith. The data compression may be executed by the use of an LZ method, a modified LZ method, such as LZW, LZSS, or the like.

REFERENCES:
patent: 5162838 (1992-11-01), Inuzuka et al.
patent: 5204949 (1993-04-01), Yasue et al.
Patent Abstract of Japan, vol. 014, No. 537 (E-1006), 27 Nov. 1990; JP-A-02 228156, Sep. 11, 1990.
Hans J. Busschaert, et al., "A Viable Multi Standard Rate Adapter Chip for ISDN Communications"; Electronic Circuits and Systems for Communication, ETH Zurich, Mar. 5-8, 1990; No. 5, Mar. 1990, pp. 231-242.

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