Terabit per second packet switch having assignable multiple pack

Details Terabit per second packet switch having assignable multiple pack Terabit per second packet switch having assignable multiple pack

1995-08-31

1998-03-03

Safourek, Benedict V.

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

370413, 370419, 3408255, H04L 1254

Patent

active

057243522

ABSTRACT:
A physically realizable one terabit or more ATM packet switch that has a large number of input interfaces connected to a single stage switching fabric which is in turn connected to a number of output modules, generally according to the growable packet switch architecture. This ATM packet switch is different from other growable packet switches in that it has a single stage switch fabric controlled by an out-of-band controller, yet it has significantly reduced complexity with respect to comparably sized electronic crossbar switches or their isomorphs. The out-of-band controller has multiple priority levels in order to provide high priority users with a near certainty that their packets will be successfully routed, while delivering an acceptably low packet or cell loss probability to users at the lowest priority level.

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