Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
2001-04-18
2003-01-07
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S501000, C257S506000, C257S446000
Reexamination Certificate
active
06504225
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor processing, and more particularly to a circuit device for detecting the presence of conductor structures in insulation structure seams and to methods of making the same.
2. Description of the Related Art
The implementation of integrated circuits involves connecting isolated circuit devices through specific electrical pathways. Where integrated circuits are implemented in silicon, it is necessary, therefore, to initially isolate the various circuit devices built into the silicon substrate from one another. The circuit devices are thereafter interconnected to create specific circuit configurations through the use of global interconnect or metallization layers and local interconnect layers.
Local oxidation of silicon (“LOCOS”) and trench and refill isolation represent two heavily used isolation techniques for both bipolar and metal oxide semiconductor (“MOS”) circuits. In a conventional semi-recessed LOCOS process, a thin pad oxide layer is thermally grown on a silicon substrate surface and coated with a layer of chemical vapor deposition (“CVD”) silicon nitride. The active regions of the substrate are then defined with a photolithographic step. The nitride layer is then dry etched and the pad oxide layer is wet or dry etched with the photoresist left in place to serve as a masking layer for a subsequent channel stop implant. After the channel stop implant, field oxide regions are thermally grown by means of a wet oxidation step. The oxidation of the silicon proceeds both vertically into the substrate and laterally under the edges of the nitride layer, resulting in the formation of structures commonly known as bird's beaks.
In trench-based isolation structures, a damascene process is used to pattern and etch a plurality of trenches in the silicon substrate. The trenches are then refilled with a CVD silicon dioxide or doped glass layer that is planarized back to the substrate surface using etchback planarization or chemical mechanical polishing (“CMP”).
Although conventional trench and refill isolation techniques eliminate the difficulties associated with bird's beak formation in LOCOS processes, certain difficulties may remain.
One of these is the formation of unwanted seams or voids in the upper reaches of the trench isolation structure. During the plethora of processing steps that follow isolation formation, these seams may become filled with conducting materials, such as doped polysilicon, refractory metal silicides, or metals. Such unwanted conductor structures can lead to shorts between active devices.
The causes of seam formation are legion. In some cases, etch removal of protective films present over active device regions during trench isolation formation may attack the upper surface of the isolation structure and produce a seam. Rip-out during CMP can also produce a seam. Finally, a void may form during CVD of the trench fill material. Such voids may remain open during CVD or sometimes close over with a thin top layer. The thin top layer may be thereafter removed inadvertently during etching or CMP.
Conventional attempts to address seam formation on isolation structures focus on overetching to eliminate any material pooling in the seam, on defect inspection and on electrical testing. Each technique has drawbacks. Overetching cannot always guarantee complete material removal from a seam. Defect inspection may prove difficult since the seams often appear in the most densely populated areas of a chip. In these areas, discrimination of sometimes very small scale seam-located conductor structures can challenge the most sophisticated inspection tools. Finally, conventional electrical testing can detect the presence of an electrical fault. However, conventional electrical testing is done at a relatively late stage in die processing and is not tailored to identify and characterize seam-related electrical anomalies.
The present invention is directed to overcoming or reducing the effects of one or more of the foregoing disadvantages.
SUMMARY OF THE INVENTION
In accordance with one aspect of the present invention, a circuit device is provided that includes an insulating structure positioned on a substrate and a first conductor structure that has a first member positioned on the insulating structure. A second conductor structure is provided that has a second member positioned on the insulating structure. The second member projects toward the first conductor structure and the first member projects toward the second conductor structure, but the first and second conductor structures are not in physical contact. A current flowing between the first and second conductor structures when a bias is applied between the first and second conductor structures is indicative of a third conductor structure present on the insulating structure and contacting the first and second members.
In accordance with another aspect of the present invention, a circuit device is provided that includes an isolation structure positioned on a substrate and a first conductor structure that has a first member positioned on the isolation structure. A second conductor structure is provided that has a second member positioned on the isolation structure. The second member projects toward the first conductor structure and the first member projects toward the second conductor structure, but the first and second conductor structures are not in physical contact. A current flowing between the first and second conductor structures when a bias is applied between the first and second conductor structures is indicative of a third conductor structure present on the isolation structure and contacting the first and second members.
In accordance with another aspect of the present invention, a circuit device is provided that includes an isolation structure positioned on a substrate and a first conductor structure that has a first plurality of members positioned in spaced-apart relation on the isolation structure to define a first plurality of gaps. A second conductor: structure is provided that has a second plurality of members positioned in spaced-apart relation on the isolation structure. The second plurality of members project toward the first conductor structure and into one or more of the plurality of gaps, but the first and second conductor structures are not in physical contact. A current flowing between the first and second conductor structures when a bias is applied between the first and second conductor structures is indicative of a third conductor structure present on the isolation structure and contacting at least one of the first plurality of members and at least one of the second plurality of members.
In accordance with another aspect of the present invention, an integrated circuit is provided that includes a substrate, a plurality of transistors on the substrate, and an isolation structure positioned on the substrate. A first conductor structure is provided that has a first member positioned on the isolation structure. A second conductor structure is provided that has a second member positioned on the isolation structure. The second member projects toward the first conductor structure and the first member projects toward the second conductor structure, but the first and second conductor structures are not in physical contact. A current flowing between the first and second conductor structures when a bias is applied between the first and second conductor structures is indicative of a third conductor structure present on the isolation structure and contacting the first and second members.
In accordance with another aspect of the present invention, a method of processing a substrate is provided that includes forming an insulating structure on the substrate and forming first conductor structure that has a first member positioned on the insulating structure. A second conductor structure is formed that has a second member positioned on the insulating structure such that the second member projects toward the first c
Cooper David E.
McCarthy Michael
Sale Denise C.
Advanced Micro Devices , Inc.
Honeycutt Timothy M.
Huynh Andy
Nelms David
LandOfFree
Teos seaming scribe line monitor does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Teos seaming scribe line monitor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Teos seaming scribe line monitor will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3006812