TEOS intermetal dielectric preclean for VIA formation

Details TEOS intermetal dielectric preclean for VIA formation TEOS intermetal dielectric preclean for VIA formation

1991-06-07

1993-06-15

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437946, 437981, 437238, 156644, 156646, 156650, 156653, H01L 2118, B23P 1500, B44C 122

Patent

active

052197913

ABSTRACT:
A method of precleaning a TEOS oxide layer of a semiconductor device formed by a dep-etch process in order to promote photoresist adhesion to the TEOS oxide layer. The method comprises exposing the TEOS oxide layer to a solution comprising: NH.sub.4 F, buffered HF, and ethylene glycol.

REFERENCES:
patent: 4176003 (1979-11-01), Brown et al.
patent: 4872947 (1989-10-01), Wang et al.
patent: 4956035 (1990-09-01), Sedlak
patent: 4980301 (1990-12-01), Harrus et al.
patent: 5091049 (1992-02-01), Campbell et al.
"Sixth International IEEE VLSI Multi-Level Interconnection Conference," A Single Pass, In situ Planarization Process Utilizing TEOS for Double Poly, Double Metal CMOS Technologies, by Sunil Mehta & Gian Sharma, 1989.
1989 VMIC Conference of IEEE, In-situ Planarization of Dielectric Surfaces Using Boron Oxide, by Jeffrey Marks, Cam Lau and David Wang, Applied Materials, Santa Clara, Calif.

Affiliated with

Also associated with

Rating

TEOS intermetal dielectric preclean for VIA formation does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with TEOS intermetal dielectric preclean for VIA formation, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and TEOS intermetal dielectric preclean for VIA formation will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1042343