TEOS assisted oxide CMP process

Details TEOS assisted oxide CMP process TEOS assisted oxide CMP process

2006-08-15

2006-08-15

Deo, Duy-Vu N (Department: 1765)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S427000, C438S690000, C438S691000

Reexamination Certificate

active

07091103

ABSTRACT:
CMP of integrated circuits containing DRAM arrays with trench capacitors fill the trenches with oxide, resulting in a an array of oxide structures that is dense compared with the concentration in the surrounding support structures and therefore has a higher loading. A conformal layer is deposited over the wafer, increasing the loading in the array, but filling in spaces between active areas. A blanket etch removes material in both the array and the supports. A block etch balances the amount of material in the array and the supports. A supplementary oxide deposition in the array fills spaces between the structures to a nearly uniform density.

REFERENCES:
patent: 6001696 (1999-12-01), Kim et al.
patent: 6015755 (2000-01-01), Chen et al.
patent: 6319796 (2001-11-01), Laparra et al.
patent: 6617251 (2003-09-01), Kamath et al.
patent: 2003/0013270 (2003-01-01), Seitz

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