Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
1998-06-29
2001-02-13
Metjahic, Safet (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S765010
Reexamination Certificate
active
06188232
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to semiconductor manufacture and more particularly to a high speed temporary package and interconnect for testing semiconductor dice, to a method for testing dice using the interconnect, and to a method for fabricating the interconnect.
BACKGROUND OF THE INVENTION
Semiconductor dice must be tested during the manufacturing process to evaluate various electrical parameters of the integrated circuits formed on the dice. Accordingly, different testing procedures have been developed by semiconductor manufacturers for testing semiconductor dice. Standard tests for gross functionality are typically performed by probe testing the dice at the wafer level using probe cards and wafer steppers. Burn-in testing is typically performed after the dice have been singulated and packaged using a burn-in oven or similar testing apparatus in electrical communication with test circuitry. Among the tests performed are dynamic burn-in, input/output leakage, speed verification, opens, shorts, refresh and a range of algorithms to verify AC parameters.
In the case of unpackaged dice, marketed by manufacturers as known good dice (KGD), temporary packages are required to house a single bare die for burn-in and other test procedures. This type of temporary package is described in U.S. Pat. Nos. 5,541,525, 5,519,332 and 5,495,179 to Wood et al.
These temporary packages typically include an interconnect component for establishing temporary electrical communication with the die. The interconnect can include a substrate with contact members for electrically contacting the bond pads or other contact locations on the die. The interconnect can also include conductors, such as metallized traces, for providing a conductive path from testing circuitry to the contact members. Interconnects for temporary packages are disclosed in U.S. Pat. Nos. 5,483,741 and 5,523,697 to Farnworth et al., incorporated herein by reference.
With advances in the architecture of semiconductor devices, it is advantageous to perform some testing of integrated circuits using very high speed testing signals. For example, testing frequencies of 500 MHz and greater are anticipated for some memory products such as DRAMS. The temporary packages and interconnects used to test dice must be capable of transmitting signals at these high speeds without generating parasitic inductance and cross coupling (i.e., “cross talk”).
Parasitic inductance and cross coupling can arise in various electrical components of the temporary packages and in the electrical interface of the interconnect with the temporary package. This can adversely effect the test procedure by causing the power supply voltage to drop or modulate during the test procedure and by causing noise and spurious signals.
For example, the conductors on the interconnect are typically wire bonded to corresponding conductive traces and terminal contacts formed on the temporary package. Capacitive coupling can occur between adjacent conductors on the interconnect and between adjacent bond wires to the conductors. High speed switching of the voltage levels in the conductors and bond wires can result in corresponding inadvertent changes in the voltage levels on nearby conductors, or bond wires, resulting in logic errors.
The problems of parasitic inductance and cross coupling can be compounded by the large number of bond pads contained on later generations of semiconductor dice. A large number of bond pads requires a corresponding large number of contact members and conductors on the interconnect. Because of their high density, it can be difficult to locate and construct the contact members and conductors without forming parasitic inductors and initiating cross talk and interconductor noise.
Because of these and other problems, there is a need in the art for improved temporary packages and interconnects for testing semiconductor dice and improved high speed testing methods.
SUMMARY OF THE INVENTION
In accordance with the invention, an improved temporary package and interconnect for testing semiconductor dice are provided. The temporary package comprises a base for retaining a single bare die and a force applying member for biasing the die against the interconnect. The interconnect mounts to the base and includes dense arrays of contact members and multi level conductors in electrical communication with the contact members. Insulating layers can be formed between adjacent levels of conductors to prevent cross talk and capacitive coupling between the conductors. Additionally, if desired, the conductors can be embedded in separate insulating layers to provide electrical isolation in both horizontal and vertical directions.
An electrical path between the contact members on the interconnect and terminal contacts on the package base can be formed by microbump tape similar to multi layered TAB tape. The microbump tape can include patterns of metal traces with microbumps (metal balls) formed in vias through the tape and electrically connected to the traces. The conductors on the interconnect can be formed with connections pads having a metallurgy for bonding to the microbumps. The microbumps can be formed of a solder alloy to provide a low resistance electrical path to the conductors that permits high speed testing.
A system for testing the die includes the interconnect, the temporary package, the microbump tape, and a testing apparatus such as a burn in board, for retaining the temporary package in electrical communication with test circuitry.
The multi level construction of the interconnect helps to overcome space limitations and permits a large number of input/output paths to be formed for a dense array of contact members. This allows testing of dice having a large number of bond pads and allows test procedures with a large number of separate input/output paths. In addition, conductors and insulating stacks on the interconnect can be used to form micro strip, embedded micro strip, and strip line conductor configurations and to tailor the electrical properties of the interconnect for high speed testing with lower noise. Furthermore, with this type of multi layered construction, impedance can be controlled and the conductors can be formed with dense peripheral arrays of connection pads.
For fabricating the interconnect, the contact members can be formed as raised members by etching a substrate and then covering the raised members with a conductive layer formed of a metal (e.g., aluminum) or a metal silicide (e.g., TiSi
2
). The contact members can also include penetrating projections for penetrating contact locations on the dice to a limited penetration depth. Alternately the contact members can be formed as indentations covered with a conductive layer and configured to electrically connect to bumped contact locations (e.g., solder bumps). The multi level conductors can be formed on the substrate using a metallization process in which patterned metal layers are alternated with insulating layers.
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Akram Salman
Farnworth Warren M.
Wood Alan G.
Gratton Stephen A.
Hollington Jermele M.
Metjahic Safet
Micro)n Technology, Inc.
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