Temporary bus master for use in a digital system having asynchro

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364228, 364240, 3642402, 3642405, 3642408, G06F 1300, G06F 1312, G06F 13362, G06F 1340

Patent

active

050620444

ABSTRACT:
A circuit embodied in a single integrated circuit, which is connected through an asynchronous communication bus to a primary bus master and a permanent bus slave, cooperates with the master and slave in a multi-master transfer of a block of data having a leading sub-block of data followed by a trailing sub-block of data. The slave operates in accord with request/acknowledge protocol by applying at least one request signal to a conductor of the bus and responding to each of a consecutive sequence of acknowledge signals on a second conductor of the bus from the master in communication of each of a consecutive sequence of concurrently-applied parallel-by-bit data carried by multiple other conductors that define a data bus portion of the communication bus. The circuit selectively responds to each of a predetermined number of acknowledge signals from the master during communication of the leading sub-block, by copying each data item of the leading sub-block, so that the leading sub-block is distributed to the circuit as it is communicated between the master and the slave. The circuit selectively responds to request signals by applying a second predetermined number of acknowledge signals to the second conductor while participating in communication of each data item of the trailing sub-block. A bi-directional buffer receives the acknowledge signals during the transfer of the leading sub-block and applies the acknowledge signals during the transfer of the trailing sub-block.

REFERENCES:
patent: 4245301 (1981-06-01), Rokutanda et al.
patent: 4365294 (1982-12-01), Stokken
patent: 4495573 (1985-01-01), Ballegeer
patent: 4587609 (1986-05-01), Boudreau et al.
patent: 4817037 (1989-03-01), Hoffman et al.

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