Temporally redundant latch for preventing single event disruptio

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

327145, 327295, H03K 513

Patent

active

061278645

ABSTRACT:
A temporally redundant latch for use in integrated circuit (IC) devices redundantly samples data output from logic or other circuitry at multiple time-shifted periods to provide multiple, independent data samples from which a correct data sample can be selected. The latch has three sampling circuits (e.g., D flip-flops or DICE latches) that sample the logic data output at three different and distinct sampling times. The latch also has a sample release circuit coupled to the sampling circuits to select and output a majority of the samples collected by the sampling circuits at a fourth time that again is different and distinct from the three sampling times. The latch affords both spatial parallelism due to the multiple parallel sampling circuits and temporal parallelism resulting from the clocking scheme involving multiple time-spaced clock signals. The temporally redundant latch is immune to upsets that might occur in the latch itself, as well as upsets that occur in the circuitry and upsets that might occur in any clocking and control signals on the IC device.

REFERENCES:
patent: 5004933 (1991-04-01), Widener
patent: 5056120 (1991-10-01), Taniguchi et al.
patent: 5150364 (1992-09-01), Negus
patent: 5886552 (1999-03-01), Chai et al.
Dodd, P.E. et al., "Critical Charge Concepts for CMOS SRAMs", IEEE Transactions on Nuclear Science, vol. 42, No. 6, Dec. 1995, pp. 1764-1771.
Buchner et al., "Comparison of Error Rates in Combinational and Sequential Logic", IEEE Transactions on Nuclear Science, vol. 44, No. 6, Dec. 1997, pp. 2209-2216.
Calin et al., "Upset Hardended Memory Design for Submicron CMOS Technology", IEEE Transactions on Nuclear Science, vol. 43, No. 6. Dec. 1996, pp. 2874-2878.
Baze et al., "Attenuation of Single Event Induced Pulses in CMOS Combination Logic", IEEE Transactions on Nuclear Science, vol. 44, No. 6, Dec. 1997, pp. 2217-2223.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Temporally redundant latch for preventing single event disruptio does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Temporally redundant latch for preventing single event disruptio, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Temporally redundant latch for preventing single event disruptio will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-199410

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.