Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Logic design processing
Reexamination Certificate
2011-07-12
2011-07-12
Whitmore, Stacy A (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Logic design processing
C716S107000, C703S013000
Reexamination Certificate
active
07979820
ABSTRACT:
In one embodiment, a method comprises retaining at least a portion of simulation results corresponding to a first simulateable partition from a previous simulation time; and using the simulation results for a second simulateable partition (or the first simulateable partition) at a current simulation time if the second simulateable partition is equivalent to the first simulateable partition and one or more input stimuli to the second simulateable partition at the current simulation time are approximately the same as the input stimuli to the first simulateable partition at the previous simulation time. Computer accessible media storing instructions that implement the method are also contemplated.
REFERENCES:
patent: 6577992 (2003-06-01), Tcherniaev et al.
patent: 7181383 (2007-02-01), McGaughy et al.
patent: 2005/0149312 (2005-07-01), McGaughy
patent: 2005/0273298 (2005-12-01), Shah
“Using Hierarchy and Isomorphism to Accelerate Circuit Simulation,” White Paper, Cadence Design Systems, Inc., 2004, 14 pages.
U.S. Appl. No. 11/257,272, filed Oct. 24, 2005, 54 pages.
Office Action from U.S. Appl. No. 11/257,272, mailed Apr. 13, 2007.
Office Action from U.S. Appl. No. 11/257,272 mailed Sep. 24, 2007.
Croix John F.
Patzer Aaron T.
Cadence Design Systems Inc.
Colandreo, Esq. Brian J
Holland & Knight LLP
Whitmore Stacy A
Whittenberger, Esq Mark H
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