Computer graphics processing and selective visual display system – Display driving control circuitry – Intensity or color driving control
Reexamination Certificate
2002-09-23
2003-07-22
Chang, Kent (Department: 2673)
Computer graphics processing and selective visual display system
Display driving control circuitry
Intensity or color driving control
C345S690000
Reexamination Certificate
active
06597372
ABSTRACT:
BACKGROUND
The invention generally relates to a temporal light modulation technique and apparatus.
Referring to
FIG. 1
, a silicon light modulator (SLM)
1
may include an array of LCD pixel cells
25
(arranged in rows and columns) that form corresponding pixels of an image. To accomplish this, each pixel cell
25
typically receives an analog voltage that controls the optical response of the pixel cell
25
and thus, controls the perceived intensity of the corresponding pixel. If the pixel cell
25
is a reflective pixel cell, the level of the voltage controls the amount of light that is reflected by the pixel cell
25
, and if the pixel cell
25
is a transmissive pixel cell, the level of the voltage controls the amount of light that passes through the pixel cell
25
.
There are many applications that may use the SLM
1
. For example, a color projection display system may use three of the SLMs
1
to modulate red, green and blue light beams, respectively, to produce a projected multicolor composite image. As another example, a display screen for a laptop computer may include an SLM
1
along with red, green and blue color filters that are selectively mounted over the pixel cells to produce a multicolor composite image.
Regardless of the use of SLM
1
, updates are continually made to the voltages of the pixel cells
25
to refresh or update the displayed image. More particularly, each pixel cell
25
may be part of a different SLM cell
20
(an SLM cell
20
a
, for example), a circuit that also includes a capacitor
24
to store a charge to maintain the voltage of the pixel cell
25
. The SLM cells
20
typically are arranged in a rectangular array
6
of rows and columns. The charges that are stored by the SLM cells
20
typically are updated (via row
4
and column
3
decoders) in a procedure called a raster scan. The raster scan is sequential in nature, a designation that implies the SLM cells
20
of a row are updated in a particular order such as from left-to-right or from right-to-left.
As an example, a particular raster scan may include a left-to-right and top-to-bottom “zig-zag” scan of the array
6
. More particularly, the SLM cells
20
may be updated one at a time, beginning with the SLM cell
20
a
that is located closest to the upper left corner of the array
6
(as shown in FIG.
1
). During the raster scan, the SLM cells
20
are sequentially selected (for charge storage) in a left-to-right direction across each row, and the updated charge is stored in each SLM cell
20
when the SLM cell
20
is selected. After each row is scanned, the raster scan advances to the leftmost SLM cell
20
in the next row immediately below the previously scanned row.
During the raster scan, the selection of a particular SLM cell
20
may include activating a particular row line
14
(often called a word line) and a particular column line
16
(often called a bit line), as the rows of the SLM cells
20
are associated with row lines
14
(row line
14
a
, as an example) and the columns of the SLM cells
20
are associated with column lines
16
(column line
16
a
, as an example). Thus, each selected row line
14
and column line
16
pair uniquely addresses, or selects, a SLM cell
20
for purposes of transferring a charge (in the form of a voltage) from one of multiple signal input lines
12
to a capacitor
24
(that stores the charge) of the selected SLM cell
20
.
As an example, for the SLM cell
20
a
that is located at pixel position (0,0) (in cartesian coordinates), a voltage may be applied to one of the video signal input lines
12
that indicates a new charge that is to be stored in the SLM cell
20
a
. To transfer this voltage to the SLM cell
20
a
, the row decoder
4
may assert (drive high, for example) a row select signal (called ROW
0
) on a row line
14
a
that is associated with the SLM cell
20
a
, and the column decoder
3
may assert a column select signal (called COL
0
) on the column line
16
a
that is also associated with the SLM cell
20
a
. In this manner, the assertion of the ROW
0
signal may cause a transistor
22
(of the SLM cell
20
a
) to couple a capacitor
24
(of the SLM cell
20
a
) to the column line
16
a
. The assertion of the COL
0
signal may cause a transistor
18
to couple one of the video signal input lines
12
to the column line
16
a
. As a result of these connections, the charge that is indicated by the voltage of the video signal input line
12
is transferred to the capacitor
24
. The other SLM cells
20
may be selected for charge updates in a similar manner.
Typically, the pixel cell
25
is formed from a liquid crystal material. Because a conventional SLM may use precise, high voltages to achieve desired gray levels from the pixel cells
25
, this high voltage requirement may be incapable with the low voltage trend of high speed digital processes, such as complementary metal-oxide-semiconductor (CMOS) processes, for example. Therefore, alternatively, some SLMs use binary voltage level pulse width modulation (PWM), a technique in which pulse width modulated signals are applied to the pixel cells.
The voltage of the pulse width modulated signal alternates between two levels: a logic one level and a logic zero level and thus, the pixel cell is either turned fully on or fully off by this signal. However, the duty cycle (the ratio of the time in which the signal has a logic one voltage level to the time in which the signal has a logic zero voltage level, for example) of the pulse width modulated signal is controlled to achieve the appearance of a gray level temporally. Thus, by using the PWM technique, precise high voltages are not used. Unfortunately, the PWM technique may require a high modulation speed and may cause excessive power to be dissipated.
Thus, there is a continuing need for an arrangement that addresses one or more of the problems that are stated above.
REFERENCES:
patent: 4020280 (1977-04-01), Kaneko et al.
patent: 5202674 (1993-04-01), Takemori et al.
patent: 5233340 (1993-08-01), Yamaguchi et al.
patent: 6232964 (2001-05-01), Lee
patent: 6239781 (2001-05-01), Fujisawa
Chang Kent
Trop Pruner & Hu P.C.
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