Coating apparatus – Program – cyclic – or time control – Having prerecorded program medium
Reexamination Certificate
2000-02-23
2001-10-02
Bueker, Richard (Department: 1763)
Coating apparatus
Program, cyclic, or time control
Having prerecorded program medium
C118S696000, C118S704000, C118S715000, C118S724000, C118S725000, C438S542000, C438S935000, C427S248100
Reexamination Certificate
active
06296709
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to high temperature processing in semiconductor manufacturing. More specifically, the invention is directed to an improved vertical diffusion furnace and method of processing.
2. Description of the Related Art
High temperature processing is used for a variety of steps in semiconductor manufacturing. After ion implantation of highly energetic ions, a high temperature annealing cycle is required to recrystalize the resulting amorphous silicon layer. Further, the same dopants are driven to proper depths within the silicon by high temperature diffusion cycles. In addition, silicon dioxide, which serves both as a dielectric for MOS devices and as an electrical isolation layer, is usually grown in an oxidation step enhanced by high temperature.
There are varying approaches to high temperature processing. Rapid thermal processing (RTP) involves placing a wafer into a chamber and providing heat via an array of lamps. Another alternative is the use of a small-batch fast-ramp furnace in which large wafer spacings allow fast temperature ramping. U.S. Pat. No. 5,001,327 to Hirasawa et al., for example, describes a furnace in which two wafers are simultaneously heat-treated and then cooled in a cooling zone at a lower portion of the reaction tube to achieve uniform heat-treatment and cooling in a short time period. High temperature processing of merely two wafers at a time, however, results in poor productivity.
The third and most cost effective approach to high temperature processing is a large-batch vertical furnace.
FIG. 1
illustrates a conventional large batch vertical diffusion furnace
10
. A processing tube
12
has tube wall
14
which is surrounded by heating elements
16
. A process gas flows in the direction
28
through a pre-heating tube
18
where it is heated to approximately the same temperature as tube wall
14
. The process gas enters gas inlet
22
at an intake port
20
and then flows into processing tube
12
through showerhead
24
. The process gas may flow out from processing tube
12
through gas outlet
26
.
A batch of more than 150 wafers may be loaded into processing tube
12
.
FIG. 2
illustrates wafers
30
loaded in silicon carbide (SiC) boats
34
which are supported by SiC boat rods
32
.
FIG. 3
illustrates a typical temperature distribution during a temperature stabilization cycle at 1373 K. Prior to the stabilization cycle at 1373 K, the tube walls and the pre-heating tube through which the process gas passed prior to entering the processing tube were ramped up from 1273 K to 1323 K at the rate of 8 K/minute and from 1323 K to 1373 K at the rate of 4 K/minute. The radial temperature of the wafers was measured. The edges of the wafer, represented by the left and right portions of the curve, have a higher temperature than the center of the wafer, represented by the middle of the curve. There is also a temperature difference between the edges of the wafer. The edge of the wafer not inside the boat red such that it was fully exposed to process gas flow, represented by the left side of the curve, has a temperature less than the temperature across the wafer where the edge is inside the boat rod and thus not fully exposed to process gas flow, represented by the right side of the curve. The temperature difference between the wafer edges, therefore, depends on whether the edge is open or inside the boat rods, and that temperature difference is significant at more than 5 degrees. In any case, both edges are at higher temperatures than is the center of the wafer.
Radial temperature nonuniformity, as illustrated in FIG.
3
and discussed above, causes thermoplastic deformation. The temperature difference results in stresses that can be sufficient to generate dislocations and form slip bands. The slip damage typically occurs at temperatures above 900° C. and also depends on the amount of oxygen precipitation inside the wafer. These defects can lead to yield loss due to leaky p-n junctions, reduced carrier mobility, and warp-induced focusing problems. The demand for faster wafer throughputs has necessitated faster ramping cycles. However, fast ramping cycles tend to cause temperature gradients. Defects in wafers are mainly generated by local temperature gradients. During temperature ramp up & ramp down, a temperature gradient in a wafer causes slip defects and dislocations in silicon.
FIG. 4
illustrates the temperature difference during the ramping cycle employed in FIG.
3
. Full diamonds represent the wafer edge inside the boat rod, while open circles represent the wafer edge away from the boat rod. Triangles represent the critical temperature for the occurrence of slip plane defects. It is evident from
FIG. 4
that the temperature stress in the wafer vastly exceeds the empirical limit for slip planes formation.
FIG. 5
illustrates a ramping cycle with three five-minute holding periods. Note that the twenty-minute stabilization cycle at 1373 K does not provide sufficient time for wafers to reach thermal equilibrium, as the temperature at the center of the wafer, Tc, differs from that of the edges of the wafer, Te.
FIG. 6
shows maximum gradients across the wafer for the ramping cycle of FIG.
5
. Since local gradients cannot be experimentally measured during processing, the radial temperature difference is used as a measure for slip occurrence.
FIG. 7
shows the temperature difference for the ramping cycle of FIG.
5
. Open circles represent the critical temperature for slip formation. Note that the slip limit is exceeded throughout the ramp up to 1373 K, while the slip limit is exceeded during ramp down from 1373 K only twice.
As defects in a wafer are mainly generated by local temperature gradients, it is desirable to have a vertical diffusion furnace which allows even heating and cooling across the wafer.
SUMMARY
The present invention provides a vertical diffusion furnace for semiconductor manufacturing processes. The furnace comprises a vertical processing tube, having a wall capable of being heated, wherein a plurality of semiconductor wafers are arranged at regular intervals; a first gas conduit connectable to the processing tube for supplying a process gas at a first temperature to the processing tube during ramp up; and a second gas conduit connectable to the processing tube, which is capable of heating a process gas to a second temperature, for supplying the preheated process gas at the second temperature to the processing tube during ramp down.
In one embodiment, the first and second gas conduits are capable of introducing the processing gas into the processing tube at flow rates sufficient to create turbulent flow.
The present invention also provides a method for the heat treatment of semiconductor wafers in a vertical diffusion furnace. A processing tube is heated to a predetermined temperature. A processing gas is introduced into the processing tube through a first gas conduit during ramp up such that the processing gas enters the processing tube at approximately room temperature. A processing gas in a second gas conduit is preheated to a temperature approximately equal to the predetermined temperature of the processing tube and introduced into the processing tube through the second gas conduit during ramp down.
In another embodiment of the method, the processing gas is introduced into the processing tube at flow rates sufficient to create turbulent flow.
REFERENCES:
patent: 4640223 (1987-02-01), Dozier
patent: 4964378 (1990-10-01), Tamba
patent: 5001327 (1991-03-01), Hirasawa et al.
patent: 5029554 (1991-07-01), Miyashita
patent: 6139642 (2000-10-01), Shimahara
patent: 62-136810 (1987-06-01), None
patent: 62-290126 (1987-12-01), None
Shigeki Hirasawa et al., “Temperature Distribution in Semiconductor Wafers Heated in a Vertical Diffusion Furnace”, IEEE Transactions on Semiconductor Manufacturing, vol. 6, No. 3, Aug. 1993, pp. 226-231.
Z. Krivokapic et al., “Temperature Nonuniformities on Silicon Wafers During Processing in Vertical Furnaces”, presented
Advanced Micro Devices , Inc.
Bueker Richard
Kwok, Esq. Edward C.
Skjerven Morrill & MacPherson LLP
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