Temperature, process and voltage variant slew rate based power u

Details Temperature, process and voltage variant slew rate based power u Temperature, process and voltage variant slew rate based power u

1995-06-01

1997-11-25

Teska, Kevin J.

Boots, shoes, and leggings

364578, 3642212, 3642756, G06F 1750

Patent

active

056921608

ABSTRACT:
A power usage simulator and method for generating a baseline power usage model for a representative sample of cells in a circuit cell library, where the baseline power model is based on signal slew rates and output load for a given of environmental conditions. The baseline power usage model is aggregated for a representative set of library cells so as to provide an accurate baseline power usage computation for all logic cells rather than for each transistor or each individual cell. Thereafter, power coefficient sensitivities to varying temperature, supply voltage and process conditions are determined for each power coefficient. Power coefficient sensitivities are measured by comparing the ratios of the measured power coefficients resulting from maintaining two of the three parameters (temperature, voltage and process) at baseline values while varying the third parameter over its entire range. In a second embodiment, the interrelationship of the parameters at values other than baseline is measured by repeating sensitivity measurements at values other than the baseline for each of the fixed parameters (previously maintained at baseline). In this second embodiment, a plurality of sensitivity terms are developed for each power coefficient and then analyzed to yield an interdependent power coefficient sensitivity. Power coefficient sensitivity information is thereafter stored to be utilized during a precomputer phase of the simulation process.

REFERENCES:
patent: 5446676 (1995-08-01), Huang et al.
patent: 5473548 (1995-12-01), Omori et al.
patent: 5481469 (1996-01-01), Brasen et al.
R.W. Phelps; "Advanced Library Characterization for High Performance ASIC"; Proceedings of the IEEE intl. ASIC Conference; 1991, pp. P15-3.1 through P15-3.4.
Michael N. Misheloff; "Improved Modelling and Characterization System for Logic Simulation"; IEEE (0-7803-0768-2) 1992, pp. 331-334.

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