Temperature-insensitive output current limiter network for...

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Amplitude control

Reexamination Certificate

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Details

C327S313000

Reexamination Certificate

active

06570431

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates in general to integrated circuits and components therefor, such as may be employed in telecommunication circuits and the like, and is particularly directed to a new and improved output current limiter circuit configuration that is effectively insensitive to variations in temperature.
BACKGROUND OF THE INVENTION
FIG. 1
schematically illustrates a complementary polarity bipolar transistor circuit that has been conventionally employed to limit, within reasonable tolerances, the output current produced by an analog integrated circuit, including but not limited to those employed in telecommunication signaling applications (such as subscriber line interface circuits (SLICs). In accordance with the illustrated architecture, an upstream analog circuit whose output current is to be limited, shown in block diagram form as ‘analog integrated circuit (IC)’
10
, has its output terminal Iout_np coupled to the base electrodes
22
and
32
of respective NPN and PNP bipolar transistors
20
and
30
, and also to one end
41
of a Vbe-bias control resistor
40
. The second end
42
of the resistor
40
is coupled in common to the emitters
23
and
33
of respective NPN and PNP transistors
20
and
30
, and to a current limited output terminal
50
, that provides a limited output current Iout_lim. NPN transistor
20
has its collector
21
coupled to a positive collector bias voltage terminal
24
, while PNP transistor
30
has its collector
31
coupled to a negative bias voltage terminal
34
.
In operation, if the output current being supplied to terminal Iout_np is derived from an NPN-type output current transistor within the analog IC
10
, then the polarity of the voltage drop across the Vbe-bias control resistor
40
will be the same as that of the base-emitter junction of the NPN transistor
20
. When this output current through the resistor
40
exceeds the Vbe of NPN transistor
20
, NPN transistor
20
turns on, and its collector begins to rob base drive from the upstream output device. This current robbing operation continues until the voltage across resistor
40
is equal to the magnitude of the base-emitter voltage of NPN transistor
20
necessary to conduct a collector current that is approximately equal the total available base drive current. Namely, at total output stage base drive,
I
out

lim×R
40
=Vbe
NPN20
.  (1)
A complementary operation occurs between Vbe-bias control resistor
40
and PNP transistor
30
when the output current originates from a PNP-type device.
Now although it is capable of effectively limiting the output current in accordance with the Vbes of the two transistors and the value of Vbe-bias control resistor
40
, the current limiter circuit architecture of
FIG. 1
is operationally imprecise, due to the fact that its components have opposite polarity temperature coefficients. In particular, the base-emitter voltages of the bipolar transistors
20
and
30
have relatively large negative temperature coefficients (typically on the order of −two millivolts per degree Centigrade), while the Vbe-bias control resistor
40
(which is customarily a low valued resistor) has a relatively large positive temperature coefficient &THgr;
R
(e.g., some number of milliohms per degree Kelvin).
When these opposite polarity temperature coefficients and the manufacturing tolerances of the components are taken into account, inordinately wide variations in the limited output current over the operating temperature range of the IC can be expected.
SUMMARY OF THE INVENTION
In accordance with the present invention, this temperature change-based lack of precision in limiting the output current of an analog IC is effectively overcome by converting each NPN and PNP associated side of the current limiting circuit of
FIG. 1
into a respective complementary polarity (N/P) bridge-configured network architecture. One arm of each bridge-configured circuit includes a first additional or auxiliary resistor, the current through which is proportional to temperature, and has a value such that the voltage across it is effective to both compensate for the negative temperature coefficient of the base-emitter voltage of that arm's (NPN or PNP) transistor, as well as to track the positive temperature variation in the Vbe-bias control resistor in a second arm of the circuit.
The second arm of the bridge-configured circuit also includes a second additional or auxiliary resistor, the voltage across which is established by a fixed current derived from a bandgap voltage device. The temperature-proportional current employed by the bandgap voltage device to generate a fixed bandgap voltage is mirrored into the temperature-proportional current supplied to the first auxiliary resistor. The fixed voltage across the second auxiliary resistor yields temperature-independent scaling of the voltage at which current limit occurs and recovers the voltage overhead penalty introduced by the voltage across the first auxiliary resistors. Because the modified limited output current circuit of the invention is effectively insensitive to temperature, its primary source of fluctuation is reduced to the tolerance of the Vbe-bias control resistor.


REFERENCES:
patent: 3600696 (1971-08-01), Grandmont
patent: 4345164 (1982-08-01), Gies
patent: 4823094 (1989-04-01), Reiffin
patent: 5057790 (1991-10-01), Landi
patent: 5963065 (1999-10-01), Alini et al.
patent: 6069534 (2000-05-01), Kobayashi

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