Miscellaneous active electrical nonlinear devices – circuits – and – External effect – Temperature
Reexamination Certificate
1996-06-07
2001-08-07
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
External effect
Temperature
C327S538000, C327S543000, C323S315000
Reexamination Certificate
active
06271710
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a circuit in which current flowing therein varies depending on a temperature (hereinafter referred to as a temperature dependent circuit), and a current generating circuit, an inverter and an oscillation circuit using the same. More specifically, the present invention relates to a temperature dependent circuit, a current generating circuit, an inverter and an oscillation circuit which are used for a DRAM (Dynamic Random Access Memory) having a self-refresh function.
2. Description of the Background Art
A DRAM is a memory in which memory cells using memory cell transistors and memory cell capacitance are arranged in an array form. Since a memory cell is a volatile element, data retained therein must be refreshed within a fixed period. In recent years, however, there has been developed a DRAM with an additional function to refresh data therein automatically by itself when set to a special mode.
This function has made it possible for users to use a RAM without taking care of refreshing data therein. At he same time, this function allows the maximum performance of the DRAM and reduction in power consumption. In other words, data is refreshed by the DRAM itself at longer intervals than prescribed, whereby the number of times to refresh data can be reduced, resulting in reduction in the number of times of DRAM operations.
FIG. 56
is a schematic block diagram showing a DRAM having such a refresh function. In
FIG. 56
, a row address strobe signal {overscore (RAS)}, a column address strobe signal {overscore (CAS)} and a write enable signal {overscore (WE)} are applied to a signal input portion
1
, from which an internal RAS signal is applied to one input terminal of multiplexer
4
. A self refresh detection circuit
2
detects a self refresh mode. More specifically, self refresh detection circuit
2
detects, as a refresh mode, a timing when tens of &mgr;sec have passed after a column address strobe signal {overscore (CAS)} falled prior to a row address strobe signal {overscore (RAS)} which is called a {overscore (CAS)} before {overscore (RAS)} (CBR) which cannot be generated at the time of a normal access. This detection signal is applied to a timer
3
as well as to multiplexers
4
and
7
as a switching signal. Timer
3
starts oscillating in response to the self refresh detection signal. An output of this timer
3
is applied to the other input terminal of multiplexer
4
and an address counter
5
. Address counter
5
counts a timer output and outputs an internal address signal to one input terminal of multiplexer
7
. An external address signal is input from an address buffer
6
to the other input terminal of multiplexer
7
. Multiplexer
7
selects the internal address signal or the external address signal and applies an X address signal and a Y address signal to a row decoder
9
and a column decoder
10
, respectively. Row decoder
9
decodes the X address signal to designate an X address of a memory cell array
8
, and column decoder
10
decodes the Y address signal to designate a Y address of memory cell
8
. External data which has been input to an I/O portion
12
is written into a memory cell at the designated address of the memory cell array, or data is read from the memory cell at the designated address in memory cell array
8
and then amplified in a sense amplifier
11
to be output to I/O portion
12
.
FIG. 57
is a timing chart illustrating a self refresh operation of the DRAM of FIG.
56
. In normal read and write operations of the DRAM of
FIG. 56
, multiplexer
4
selects an output of signal input portion
1
, and multiplexer
7
selects an external address signal of an output of address buffer
6
. In addition, an address of memory cell array
8
is designated by the external address signal.
On the other hand, in a self refresh mode, a column address strobe signal {overscore (CAS)} falls before a row address strobe signal {overscore (RAS)} falls as shown in (
a
) and (
b
) of FIG.
57
and self refresh detection circuit
2
detects lapse of tens of &mgr;sec from the fall of the row address signal {overscore (RAS)}. Timer
3
starts oscillating in response to the detection output as shown in FIG.
57
(
c
). At this time, multiplexer
4
has been switched to the side of an output of timer
3
in response to the detection output of self refresh detection circuit
2
, and applies an output of timer
3
to a read/write circuit (not shown) as an internal RAS. Address counter
5
counts an oscillation output of timer
3
, and outputs an internal address signal. Multiplexer
7
applies the internal address signal, that is, an output of address counter
5
to row decoder
9
and column decoder
10
in response to the detection output of self refresh detection circuit
2
. Row decoder
9
selects a set of word lines in response to an X address signal, and a plurality of memory cells connected thereto are refreshed automatically by sense amplifier
11
.
FIG. 58
is a circuit diagram specifically showing a timer circuit of FIG.
56
. In
FIG. 58
, timer circuit
3
is constituted by a ring oscillator. In other words, inverters
301
,
302
. . .
30
n
of the odd number of stages are connected to each other in a loop shape, constituting an oscillation stage. In addition, p channel transistors
311
,
312
. . .
31
n
are connected between power supply terminals of respective inverters
301
,
302
. . .
30
n
and a power supply line, and n channel transistors
321
,
322
. . .
32
n
are connected between ground terminals of respective inverters
301
,
302
. . .
30
n
and a ground line. These transistors are provided in order to restrict current flowing into each inverter
301
,
302
, . . .
30
n.
An n channel transistor
34
is provided to equalize the amount of current applied by transistors
311
,
312
, . . .
31
n
from the side of power supply potential of inverters
301
,
302
. . .
30
n
with the amount of current applied by transistors
321
,
322
. . .
32
n
from the side of ground potential of inverters
301
,
302
, . . .
30
n.
This n channel transistor
34
has its gate connected to a power supply line of a fixed potential, its source grounded, and its drain connected to a diode-connected p channel transistor
33
. The gate of n channel transistor
34
is connected to the gates of n channel transistors
321
,
322
. . .
32
n,
and p channel transistor
33
copies current flowing into n channel transistor
34
to supply the current to the gates of p channel transistors
311
,
312
, . . .
31
n.
An output of the ring oscillator arranged as described above has its oscillation frequency determined by current which is determined by n channel transistor
34
having a gate potential fixed to a power supply line of a fixed potential. Accordingly, oscillation at a fixed frequency is possible. However, the oscillation at a fixed frequency can be realized only when conditions are constant, and the oscillation frequency varies as the conditions changes.
For example, as shown in
FIG. 60A
, an oscillation frequency is increased as a power supply potential is varied. This is because increase in a power supply potential causes increase in a gate potential of n channel transistor
34
which is fixed to a power supply potential of a fixed potential, whereby current applied by this n channel transistor
34
is increased, resulting in increase in current flowing into inverters
301
,
302
. . .
30
n.
Furthermore, as shown in
FIG. 60B
, an oscillation frequency is reduced as a temperature is increased. This is because increase in a temperature causes reduction in a current driving ability of n channel transistor
34
, whereby current applied by this n channel transistor
34
is reduced, resulting in reduction in current flowing into inverters
301
,
302
. . .
30
n.
In addition, increase in a temperature causes increase in internal resistance of inverters
301
,
302
. . .
30
n,
whereby current is difficult to flow therein, resulting in reduction in an oscillat
Lam Tuan T.
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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