Temperature-compensated interface circuit between "OR-tied" conn

Details Temperature-compensated interface circuit between "OR-tied" conn Temperature-compensated interface circuit between "OR-tied" conn

1987-06-25

1988-12-06

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307310, 307456, 307466, H03K 19003

Patent

active

047897970

ABSTRACT:
An interface circuit (110) for interfacing between an "OR-tied" connection (P) of a programmable logic array device (10) and a TTL output buffer (36) includes a first bandgap generator (40), a high level clamp circuit (30), a second bandgap generator circuit (42), and a sensing circuit (26). The first bandgap generator (40) generates a first reference voltage (VB1) which has a positive temperature coefficient. The second bandgap generator (42) generates a second reference voltage (VB2) which has a negative temperature coefficient. A resultant base drive current (I.sub.x) is supplied to the base of a phase splitter transistor (Q2) in the output buffer (36). The resultant current (I.sub.x) is controlled by the first and second bandgap generators (40, 42), the current being higher at low temperatures and being smaller at high temperatures.

REFERENCES:
patent: 4460865 (1984-07-01), Bynum et al.
patent: 4514650 (1985-04-01), Yum
patent: 4590418 (1986-05-01), Moriarty, Jr.
patent: 4626770 (1986-12-01), Price, Jr.
patent: 4677368 (1987-06-01), Bynum
patent: 4677369 (1987-06-01), Bowers et al.
patent: 4701636 (1987-10-01), Millhollan et al.

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