Temperature compensated high speed ECL-to-CMOS logic level trans

Details Temperature compensated high speed ECL-to-CMOS logic level trans Temperature compensated high speed ECL-to-CMOS logic level trans

1989-08-25

1990-11-06

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307451, 307310, 323907, H03K 1714

Patent

active

049689053

ABSTRACT:
An emitter coupled logic (ECL)-to-complementary metal-oxide-semiconductor (CMOS) logic level translator is temperature compensated to track temperature induced shifts in the ECL logic levels. The translator includes a differential amplifier with mid-range reference voltage. A reference voltage generator supplies the reference voltage to the differential amplifier and has a temperature sensitive transistor which changes the value of the circuit output (reference) voltage ambient with temperature shifts.

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