Miscellaneous active electrical nonlinear devices – circuits – and – External effect – Temperature
Reexamination Certificate
2002-11-25
2004-07-06
Nguyen, Long (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
External effect
Temperature
C327S512000, C327S542000, C327S543000
Reexamination Certificate
active
06759893
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to temperature-compensated current sources, and more particularly, to the optimization of a current reference circuit providing temperature compensation for the generated current.
BACKGROUND OF THE INVENTION
The possibility of obtaining transistors with practically identical characteristics has given rise to a new generation of current sources known as current mirrors. A rise in the temperature leads especially to the following results: an increase in the leakage currents of the transistors used in such current reference circuits, an increase in the stored charge, and an increase in gain, etc.
These phenomena, among others, involve a modification of the intrinsic characteristics of the transistors implemented in the current sources, resulting in the copied currents not being accurate. The current generated in such a current source is therefore dependent on the temperature variations. It is difficult to obtain a current reference source giving a constant current that is not sensitive to variations in temperature. To illustrate this phenomenon, referring now to
FIG. 1
, we shall look at the drawing of a standard prior art current source using complementary metal oxide semiconductor (CMOS) technology.
The prior art current source includes three arms: b
1
, b
2
and b
3
. The middle arm b
2
is a current reference arm whose role is to fix a reference current. The third arm b
3
is an output arm in which the reference current Iref is copied. The role of the first arm b
1
is to fix a reference voltage V
1
.
The current reference arm b
2
comprises a first MOS transistor M
2
whose source electrode is connected to a voltage supply terminal VDD, and whose gate electrode and drain electrode are connected to each other. The MOS transistor M
2
therefore makes it possible to fix a reference current in the first and third arms b
1
and b
3
.
The drain electrode of the first MOS transistor M
2
is connected to the source electrode of a second MOS transistor M
5
, whose drain electrode is connected at a node N to the potential V
2
grounded by a first resistor R
1
. The first resistor R
1
is series-connected with a set of n parallel-connected elements Q
2
enabling a voltage V
3
to be fixed, with n being an integer at least equal to two. According to a preferred embodiment of the invention, each parallel-connected element Q
2
is formed by a diode. More precisely, it is a MOS transistor whose parasitic bipolar effects are used to form the diode.
The output arm b
3
of the current source includes a MOS transistor M
3
whose source is connected to the power supply terminal VDD, and whose gate is connected to the gate of the MOS transistor M
2
of the current reference arm b
2
. Thus, by copying the reference current fixed by the current reference arm (b
2
) into the current mirror M
2
, M
3
, the output current Iref of the current source is provided at the drain of the transistor M
3
.
The arm b
1
of the current source comprises a first MOS transistor M
1
whose source electrode is connected to the supply terminal VDD. The gate electrode of the transistor M
1
is connected to the gate electrode of the transistor M
2
of the current reference arm b
2
of the current source, thus forming a second current mirror. The current generated in the current reference arm b
2
is copied in the arm b
1
, and the currents flowing in the arm b
1
and in the arm b
2
are thus equal. The drain electrode of the MOS transistor M
1
is connected to the source electrode of a second MOS transistor M
4
, whose gate electrode is connected to the gate electrode of the MOS transistor M
5
of the current reference arm b
2
. Furthermore, the gate electrode of the transistor M
4
is connected to its source electrode.
Finally, the drain electrode of the transistor M
4
is grounded by an element Q
1
that is used to fix the voltage V
1
, and is identical to each of the n parallel-connected elements Q
2
of the arm b
2
. Thus, according to a preferred embodiment, Q
1
is a MOS transistor whose stray bipolar effects are used to form a diode.
The MOS transistors M
4
and M
5
make it possible for the first and second arms to be symmetrical, respectively b
1
and b
2
, and form a voltage copying circuit which permits the copying of the reference voltage V
1
fixed by the diode Q
1
at the node N at the potential V
2
of the arm b
2
, so that V
2
=V
1
.
The configuration of the MOS transistors M
1
, M
2
, M
4
and M
5
as described above therefore makes it possible to obtain equal currents I
1
and I
2
respectively flowing in the arms b
1
and b
2
of the current source, as well as equal voltages V
1
and V
2
, according to a well-known principle of operation that needs no detailed description herein.
Consequently, the difference in potential &Dgr;V at the terminals of the resistor R
1
may be expressed as follows:
Δ
V
=
V2
-
V3
=
V1
-
V3
According to a standard equation governing operation of the bipolar transistors, we have:
V
1
=
VT
*ln(I
1
/Is
1
), and
V
3
=
VT
*ln(I
2
/
n
*Is
2
)
Is
1
and Is
2
are the saturation currents of the diode-mounted transistors Q
1
and Q
2
, and VT is the thermal voltage which physically corresponds to the ratio between the coefficient of diffusion of the charges and the mobility of the charges, and can be expressed as follows:
VT
=
k
*
T
q
The variable k is Boltzman's constant, T is the temperature (in degrees Kelvin) and q is the elementary charge.
Numerically, k=1,381*10
−23
J*K
−1
(Joules per Kelvin) and q=1,602*10
−19
C (coulombs). Consequently:
Δ
V
=
k
*
T
*
ln
q
[
I1
Is1
*
n
*
Is2
I2
]
The diode-mounted transistors Q
1
and Q
2
are advantageously designed to be identical so as to present the same physical properties, hence Is
1
=Is
2
. Furthermore, we have already seen above that, by current copying, the currents I
1
and I
2
are identical. The potential difference &Dgr;V at the terminals of the resistor R
1
can then be expressed as follows:
Δ
V
=
k
*
T
q
*
ln
(
n
)
The current I
2
, generated by the potential difference &Dgr;V at the terminals of the resistor R
1
and flowing through the arm b
2
, is expressed conventionally by the following relationship:
I2
=
Δ
V
R1
Now, by copying the current in the MOS transistor M
3
, the currents Iref and I
2
are identical. Consequently:
Iref
=
k
*
T
q
*
ln
(
n
)
/
R1
(
1
)
Here we can understand the value of placing n transistors Q
2
in parallel since, without this characteristic and through simplifying the equations, the output current Iref of the current reference source would be theoretically zero.
The above relationship (1) clearly shows that the current Iref varies linearly with the temperature T (in the ideal case where the value of the resistor R
1
does not vary with the temperature), and the variation of the current Iref as a function of the temperature is expressed according to the following expression:
δ
Iref
δ
T
=
k
q
*
ln
(
n
)
/
R1
A prior art current source of this kind therefore raises a problem of stability of the reference current given in relation to the temperature. This aspect may prove to be an inherent defect in many applications.
SUMMARY OF THE INVENTION
An object of the present invention is to overcome the drawbacks of the prior art by improving the current sources of the type described in
FIG. 1
so that the given reference current is independent of the temperature.
This and other objects, advantages and features according to the present invention are provided by implementation of a current reference circuit whose temperature-related stability depends directly on a ratio of resistances, enabling compensation for the temperature-related variations in the reference current based upon the respective resistance values.
The invention therefore relates to a temperature-compensated current source comprising a
Ferrand Olivier
Gailhard Bruno
Jorgenson Lisa K.
Nguyen Long
STMicroelectronics SA
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