Temperature compensated CMOS to ECL translator

Details Temperature compensated CMOS to ECL translator Temperature compensated CMOS to ECL translator

1985-12-16

1987-04-07

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307446, 307297, 307310, H03K 1714

Patent

active

046563750

ABSTRACT:
The present invention is a temperature compensating circuit adapted for use with a CMOS to ECL interfacing circuit which uses one normally unused ECL logic gate, formed on a chip of many ECL logic gates for generating the supply voltages for the level interfacing circuit such that the output voltage levels from the interfacing circuit will automatically track with the temperature experienced by the chips' ECL logic gates.

REFERENCES:
patent: 4220877 (1980-09-01), Giordano
patent: 4472647 (1984-09-01), Allgood et al.
patent: 4477737 (1984-10-01), Ulmer et al.
patent: 4488064 (1984-12-01), Vance
patent: 4527078 (1985-07-01), Smith
patent: 4540900 (1985-09-01), Early et al.
patent: 4620115 (1986-10-01), Lee et al.
Gersbach, "Voltage Level Translation Circuit", IBM T.D.B., vol. 18, No. 1, Jun. 1975, pp. 71-72.

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