Miscellaneous active electrical nonlinear devices – circuits – and – External effect – Temperature
Reexamination Certificate
2000-06-23
2002-03-19
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
External effect
Temperature
C327S359000
Reexamination Certificate
active
06359499
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to analog circuits such as multipliers, adaptive filters, function generators, modulators, and neural networks. More particularly, this invention relates to compensation circuits incorporated with analog circuits to offset deviation in operation of the analog circuit due to variations in temperature and process.
2. Description of Related Art
Analog function circuits such as multipliers, adaptive filters, function generators, modulators, and neural networks, as is known in the art, produce a voltage output, which is proportional to an arithmetic function of two voltage inputs. As semiconductor processing has improved, more and varied circuits are formed on a semiconductor substrate. This has mandated the creation of libraries of analog function circuits or analog function cores.
FIG. 1
shows a system diagram of an analog function core. There are two differential voltage inputs &ngr;x, &ngr;y, and one differential voltage output &ngr;out. A load resistor RL is connected between the inverted and non-inverted output the differential voltage output &ngr;out. The differential output voltage &ngr;out is developed across a load resistor, RL and is determined by the formula:
&ngr;out=kF(&ngr;
x
&ngr;
y
) EQ. 1
where:
k is a constant of proportionality or scaling
factor.
F is the arithmetic function to be performed on the two differential input signals &ngr;x and &ngr;y.
The load resistor RL of
FIG. 1
can be formed of the two load resistors RL
1
and RL
2
as shown in FIG.
2
. The load resistor RL
1
is connected between the inverting output (−) of the differential output voltage &ngr;out and the common mode biasing voltage source Vcm. The load resistor RL
2
is connected between the non-inverting output (+) of the differential output voltage vout and the common mode biasing voltage source Vcm.
The voltage level present at the inverted (−) output terminal of the differential output &ngr;out is determined as:
&ngr;out−=Iout
1
*RL
1
+Vcm where:
I
out1
is the output current and is determined as a function of the two differential input signals
&ngr;x and &ngr;y.
RL
1
is the resistance value of the load resistor. Conversely, the voltage level present at the non-inverted (+) output terminal of the differential output &ngr;out is determined as:
&ngr;out+=Iout
2
*RL
2
+Vcm
where:
I
out2
is the output current and is determined as a function of the two differential input signals
&ngr;x and &ngr;y.
RL
2
is the resistance value of the load resistor.
FIG. 3
shows an example of an analog function circuit implemented as a voltage multiplier with differential voltage inputs and a voltage output across a load resistor. The non-inverting input &ngr;x+ of the first differential voltage input &ngr;x is connected to the gate of one of the n-type metal oxide semiconductor (MOS) transistors M
1
of a parallel connected pair of n-type MOS transistors M
1
and M
2
. The gate of the second n-type MOS transistor M
2
of the parallel connected pair of n-type MOS transistors M
1
and M
2
is connected to the inverting input &ngr;x− of the first differential voltage input &ngr;x. The commonly connected sources of the parallel connected pair of n-type MOS transistors M
1
and M
2
are connected to a first terminal of a current source Ib
3
. The second terminal of the current source Ib
3
is connected to a ground reference point. The commonly connected drains of the parallel connected pair of n-type MOS transistors M
1
and M
2
are connected to a first terminal of a current source Ib
1
. The second terminal of the current source Ib
1
is connected to a power supply voltage source V
DD
. The junction of the commonly connected drains of the parallel connected pair of n-type MOS transistors M
1
and M
2
and the first terminal of a current source Ib
3
form the output terminal containing the inverted output (−) of the differential output voltage &ngr;out.
The non-inverting input &ngr;y+ of the first differential voltage input &ngr;y is connected to the gate of one of the n-type metal oxide semiconductor (MOS) transistors M
3
of a parallel connected pair of n-type MOS transistors M
3
and M
4
. The gate of the second n-type MOS transistor M
4
of the parallel connected pair of n-type MOS transistors M
3
and M
4
is connected to the inverting input &ngr;y− of the second differential voltage input &ngr;y. The commonly connected sources of the parallel connected pair of n-type MOS transistors M
3
and M
4
are connected to a first terminal of a current source Ib
4
. The second terminal of the current source Ib
4
is connected to a ground reference point. The commonly connected drains of the parallel connected pair of n-type MOS transistors M
3
and M
4
are connected to a first terminal of a current source Ib
2
. The second terminal of the current source Ib
2
is connected to a power supply voltage source V
DD
. The junction of the commonly connected drains of the parallel connected pair of n-type MOS transistors M
3
and M
4
and the first terminal of a current source Ib
2
form output terminal containing the non-inverted output (+) of the differential output voltage vout.
The load resistor RL
1
is connected between the inverting output (−) of the differential output voltage &ngr;out and the common mode biasing voltage source Vcm. The load resistor RL
2
is connected between the non-inverting output (+) of the differential output voltage vout and the common mode biasing voltage source Vcm.
The gates of the parallel connected pair of n-type MOS transistors M
1
and M
2
and the gates of the parallel connected pair of n-type MOS transistors M
3
and M
4
are biased externally with a constant voltage source VB (not shown) to cause the parallel connected pair of n-type MOS transistors M
1
and M
2
and the parallel connected pair of n-type MOS transistors M
3
and M
4
to operate in the saturation region. This insures that any voltage developed from the drains to the sources of the parallel connected pair of n-type MOS transistors M
1
and M
2
or the parallel connected pair of n-type MOS transistors M
3
and M
4
does not effect the saturation drain-to-source current Ids through the parallel connected pair of n-type MOS transistors M
1
and M
2
or the parallel connected pair of n-type MOS transistors M
3
and M
4
.
The drain-to-source saturation current Ids
sat
of each of the parallel connected pair of n-type MOS transistors M
1
and M
2
or the parallel connected pair of n-type MOS transistors M
3
and M
4
is found by the formula:
Ids
sat
=K(V
GS
−V
T
)
2
where:
VGS is the gate-to-source of each MOS transistor.
VT is the threshold voltage at which MOS transistor begins to conduct or turn-on.
K is a process constant found as the function
K
=
μ
s
(
C
ox
2
)
(
W
L
)
where:
&mgr;
s
is the mobility of the bulk doped semiconductor material that forms the channel.
C
ox
is the capacitance of the gate oxide of the MOS transistors.
(
W
L
)
is the width-to-length ratio of the MOS transistors.
As can be shown from Einstein's Relationship, the mobility &mgr;
s
of the semiconductor material is dependent upon the absolute temperature of operation. Further, any changes in the process that effects the doping of the semiconductor material will further change the value of the mobility &mgr;
s
of the semiconductor material. Additionally, process changes may effect the geometric values of the width-to-length ratio
(
W
L
)
,
as well as the thickness of the insulating material that forms the gate oxide, which will change the values of the capacitance C
ox
.
It can be shown that the output currents I
out1
and I
out2
can be calculated by the formula:
I
out1
=
I
out2
=
μ
n
(
C
ox
)
(
W
L
)
*
v
x
*
v
y
where:
&mgr;
n
is the mobility of the bulk doped semiconductor material that forms the channel.
C
ox
is the capacitance of the gate oxide of the parallel connected pair of n-type MOS
Cunningham Terry D.
Janofsky Eric B.
Marvell International Ltd.
Tra Quan
LandOfFree
Temperature and process independent CMOS circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Temperature and process independent CMOS circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Temperature and process independent CMOS circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2855354