Television synchronizing arrangement

Details Television synchronizing arrangement Television synchronizing arrangement

1988-03-29

1989-08-08

Groody, James J.

Facsimile and static presentation processing

Facsimile

Specific signal processing circuitry

358158, H04N 504

Patent

active

048558281

ABSTRACT:
A phase-lock-loop circuit of a two-loop deflection arrangement is located in a first integrated circuit. The phase-lock-loop circuit generates a first signal at 32Xf.sub.H that is capacitively coupled to a tank circuit. A regenerative amplifier stage that is located in a second integrated circuit has an input terminal that is coupled to the tank circuit and an output terminal for producing a second signal. During normal operation, the second signal is synchronized to the first signal. The second signal is utilized in a phase-control-loop circuit of the two-loop deflection arrangement for generating a synchronized deflection current in a deflection winding.

REFERENCES:
patent: 3575666 (1971-04-01), Wantagh
patent: 3891800 (1975-06-01), Janssen et al.
patent: 4292654 (1981-09-01), Steckler et al.
patent: 4769705 (1988-09-01), Lendaro
A data sheet of a linear integrated circuit CA3210E and CA3223E of the RCA Corporation published May, 1982, entitled, TV Horizontal/Vertical Countdown Digital Sync System.
U.S. Patent Application No. 068,085, filed 6/30/87, entitled Deflection Synchronizing Apparatus, in the name of J. B. Lendaro, the applicant of the above-captioned patent application.

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