Television signal tuning device

Television – Receiver circuitry – Tuning

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Details

348732, 348725, 348735, H04N 550

Patent

active

057710805

ABSTRACT:
A television signal tuning device having a memory which is adapted to store central frequency data for starting a synchronizing-signal detecting operation for all the channels and frequency division ratio data thereof. In a data presetting operation for each of the channels, a CPU causes a phase-locked loop circuit to perform a phase-locking operation for every data piece of the central frequency data or frequency division ratio data thereof which are stored in the memory for each channel. When the CPU detects a synchronizing signal from a video signal processing circuit in any one of the phase-locking operations which are successively performed by the phase-locked loop circuit, the CPU immediately renews the channel number and the tuning data thereof in the memory without performing the detection of an AFC variation. This feature greatly reduces the period of time required for the data presetting operation for each channel.

REFERENCES:
patent: 4038689 (1977-07-01), Rzeszewski
patent: 4106059 (1978-08-01), Henderson
patent: 4337486 (1982-06-01), Akutsu
patent: 4360832 (1982-11-01), Rzeszewski
patent: 4451850 (1984-05-01), Kamemoto
patent: 4743968 (1988-05-01), Mogi et al.
patent: 4751574 (1988-06-01), Mogi et al.
patent: 5034819 (1991-07-01), Tsukagoshi
patent: 5107335 (1992-04-01), Nishiyama et al.

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