Television – Basic receiver with additional function
Reexamination Certificate
1999-05-25
2001-09-11
Hsia, Sherrie (Department: 2614)
Television
Basic receiver with additional function
C348S563000, C348S569000, C348S598000, C348S600000
Reexamination Certificate
active
06288750
ABSTRACT:
TECHNICAL FIELD
The present invention relates to television signal processors, and more specifically to a television signal processor processing a received broadcast wave and generating a television signal.
BACKGROUND ART
In recent years, due to digitalization of television broadcasting, various needs or services which have been beyond imagination in general broadcasting are beginning to emerge. As to a channel which only broadcasts movie programs, for example, a technology of copy guard is important to protect a copyright so as not to allow an unlimited copy on the receiver. Recently, therefore, it was proposed to multiplex information such as copy guard into a digital broadcast wave as additional information and to carry the copy guard in the wave so as to allow the receiver to utilize the same. Such additional information is classified according to a standard such as CGMS (IEC1880) and WSS (ETS300, 294). As to methods how to utilize the additional information, various methods are now under consideration.
The digital broadcast wave is inputted to the receiver in the form of a bit stream. Therefore, when the receiver is going to utilize the aforementioned additional information, the receiver first recognizes the additional information multiplexed into the digital broadcast wave, and separates the same. Thereafter the receiver generates an analog video signal from the digital broadcast wave, and then inserts the separated additional information into a retrace interval of the analog video signal to output. By performing such processing, it becomes possible to utilize the additional information in various types of peripheral equipment (for example, a video tape recorder) on the receiver. The aforementioned series of signal processing can be executed by a television signal processor illustrated below.
FIG. 8
shows a block diagram which is an exemplary conventional television signal processor
100
. The television signal processor shown in
FIG. 8
is formed by a decoding part
101
, a CPU interface (hereinafter, referred to as CPUI/F)
103
, a RAM interface (hereinafter, referred to as RAMI/F)
105
, video data reading part
106
, OSD data reading part
107
, a horizontal/vertical synchronous pulse generating part
108
, a video data line buffer
109
, an OSD data line buffer
110
, combining part A
111
, a CGMS timing generating part
112
, a CGMS data buffer
113
and a combining part B
114
.
The decoding part
101
generates video data by processing an inputted video stream, and then outputs the same to a work RAM
102
through the RAMI/F
105
. The work RAM
102
stores the video data. Referring to
FIG. 8
, a CPU
104
shown outside the conventional television signal processor generates OSD data. Herein, OSD (On Screen Display) stands for a channel, a receiving mode, a volume, characters of text broadcasting and the like displayed on a currently operating television screen. The OSD is generated on the basis of the OSD data generated by the CPU
104
. The OSD data generated by the CPU
104
is inputted to the work RAM
102
through the CPUI/F
103
and the RAMI/F
105
. The work RAM
102
stores the inputted OSD data.
The video data reading part
106
reads the video data stored in the work RAM
102
at prescribed timing. The read timing at this time is defined on the basis of a read timing signal for the work RAM
102
inputted from the CPU
104
through the CPUI/F
103
and the RAMI/F
105
, and a vertical pulse and a horizontal pulse generated by the horizontal/vertical synchronous pulse generating part
108
. The video data read from the work RAM
102
is temporarily stored in the video data line buffer
109
. The OSD data reading part
107
reads the OSD data from the work RAM
102
in a manner similar to the above. The read OSD data is temporarily stored in the OSD data line buffer
110
.
The combining part A
111
combines the video data inputted from the video data line buffer
109
and the OSD data inputted from the OSD data line buffer
110
. Additional information (here assumed to be CGMS) separated from the broadcast wave inputted from the CPU
104
through the CPUI/F
103
is temporarily stored in the CGMS data buffer
113
. The CGMS timing generating part
112
generates a synthetic timing signal on the basis of the horizontal synchronous pulse and the vertical synchronous pulse generated by the horizontal/vertical synchronous pulse generating part
108
. In the combining part
114
, the CGMS data is synchronized with the synthetic timing signal generated by the CGMS timing generating part
112
, and is combined with the video data with which the OSD data was combined.
As described above, for the conventional television signal processor, the second combining part
114
further combining the additional information such as copy guard (here CGMS) into the video data with which the OSD data has been combined was required in addition to the first combining part
111
combining the OSD data to the video data. This results in a complicated structure and a higher cost.
Further, the conventional television signal processor has been aimed at receiving only a digital broadcast wave of a predetermined standard. Therefore, the synthetic timing for the video data, the OSD data and the additional information is fixedly set. Consequently, if the standard of the received digital broadcast wave is different from the previously planned standard, the conventional television signal processor cannot recognize such change, and accordingly cannot combine the video data, the OSD data and the additional information at proper timing.
Therefore, an object of the present invention is to provide a television signal processor which can, even if the standard of a received broadcast wave changes, flexibly cope with such change with a simpler structure and a lower cost.
SUMMARY OF THE INVENTION
The present invention has, in order to attain the aforementioned object, the following features.
A first aspect of the present invention is directed to a television signal processor processing a received broadcast wave and generating a television signal. The processor comprises:
a storage part for storing video data and additional information separated from the received broadcast wave and OSD data generated on a receiver;
a reading part for respectively reading the video data, the additional information and the OSD data from the storage part;
a standard detecting part for detecting a standard of the received broadcast wave;
a timing controlling part for respectively controlling the timing of the reading part for reading the video data, the OSD data and the additional information from the storage part in correspondence to the standard detected by the standard detecting part; and
a combining part for combining the video data, the OSD data and the additional information read by the reading part to output the combined data as a television signal.
As described above, in the first aspect, the standard of the received broadcast wave is detected so as to respectively control timing for reading the video data, the OSD data and the additional information from the storage part in correspondence thereto, whereby, even if the standard of the received broadcast wave changes, the video data, the OSD data and the additional information can be combined regularly at proper timing in correspondence to such change.
Conventionally, two steps of synthetic processing are included, first combining video data and OSD data in an effective display area and thereafter combining additional information in the retrace interval. In the first aspect, on the other hand, the video data, the OSD data, and the additional information are respectively read from a single storage part at prescribed timing and then combined without differentiating between the effective display area and the retrace area, whereby synthetic processing of the video data, the OSD data, and the additional information in a single combining part can be achieved.
A second aspect of the present invention, which is an aspect dependent on the first aspect, is characteriz
Uehara Hirotoshi
Yamada Mikihiko
Hsia Sherrie
Matsushita Electric - Industrial Co., Ltd.
Wenderoth , Lind & Ponack, L.L.P.
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