Television – Basic receiver with additional function – Multimode
Reexamination Certificate
1998-09-29
2002-03-05
Lee, Michael (Department: 2614)
Television
Basic receiver with additional function
Multimode
C348S558000, C348S554000
Reexamination Certificate
active
06353460
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a television receiver; a video signal processing device, an image processing device, and an image processing method.
2. Description of the Related Art
In recent years, the methods of broadcasting television signals have been diversified. For instance, not only have NTSC (National Television System Committee) signals been broadcasted using a ground wave but also both NTSC signals and high-definition signals have been broadcasted using a broadcasting satellite (BS). Further, just recently, digital signals have been broadcasted using a communication satellite (CS).
With the diversified methods of broadcasting, television receivers are demanded to have a capability of receiving various types of signals from such diversified broadcasting methods to display corresponding images.
Each of the different broadcasting methods uses a video format which is different from one another. For example, the NTSC signal broadcasting uses a video format of 525 horizontal scanning lines/interlace scanning, while the high-definition signal broadcasting uses a video format of 1125 horizontal scanning lines/interlace scanning. Further, in recent years, television receivers have been requested to display video signals having video formats of VGA (video graphics array) and SVGA (super VGA) which are output from computes. As such, the demands on the display function of television receivers have increasingly become strong.
When a television receiver capable of displaying video signals having a variety of video formats is attempted to be realized, one may consider providing different conversion devices for input signals having different image formats. Such a configuration, however, requires the same number of conversion devices as that of the possible different image formats, thereby increasing the circuits size and the cost.
A conventional image processing device for performing digital image processing for video signals such as television signals is shown in FIG.
26
. Referring to
FIG. 26
, the image processing device includes a digital signal processing circuit
2200
constructed to perform a predetermined image processing for video signals and at least one field memory and/or frame memory
2202
.
In the case of a moving-image real-time processing, for example, a frame memory
2202
A and a field memory
2202
B are used for motion detection, while a frame memory
2202
C is used for motion adaption interpolation. An additional frame memory (not shown) may be used for time-axis conversion for converting a high-definition signal into an NTSC signal, for example.
Thus, a conventional digital image processing circuit heads more field memories or frame memories as more types of image processing are required. This is disadvantageous in the aspects of reducing the cost and size of the device. Dynamic random access memories (DRAMs) having a capacity of 1 to 2 M bits are used for general type field memories and frame memories. These DRAMs are extremely small in memory capacity compared with presently mainstream 10M-bit and 54M-bit dynamic RAMs, but are not so different in cost and chip size from the latter.
As the number of field memories and/or frame memories increases; the number of terminal pins of the digital signal processing circuit
2200
increases propertionally, thereby increasing the size of the resultant IC package.
Another problem is that the system with the above configuration is poorly adaptive to a variety of applications. For example, a system constructed for the NTSC signal using field memories having a capacity of 1.5 M bits is not used for the high-definition signal which needs field memories having a capacity of about 4 M bits.
Moreover, the usage of each of such a number of field memories and/or frame memories in restricted or specified in accordance with functions defined by a processing section of the digital signal processing circuit
2200
. Such a conventional image processing device therefore generally fails to be used for a variety of applications.
Conventionally, therefore, when one television receiver is intended to receive a variety of video signals such as an NTSC signal, a RS signal, a high-definition signal, and a signal output from a computer, it is required to incorporate all of the different types of digital signal processing circuits, together with relevant field/frame memories, exclusive for respective types of video signals. The resultant device is extremely high in cost and large in size.
In addition to the current demands being placed on the digital signal processing circuitry, with the onset of digital broadcasting and the enhancement of the broadcasting image quality, a video signal processing circuit incorporated in a television receiver and the like similarly has been demanded to have a function of processing video signals having different formats. Moreover, such a video signal processing circuit has been demanded to have a function of displaying as such information as possible simultaneously, such as a double-screen display end a multi-screen display. Under these circumstances, a single-instruction multiple-data (SIMD) type video signal processor has been used as the video signal processing circuit.
The SIMD video signal processor processes a video signal for each horizontal scanning line, and includes N processor elements PE
1
to PE
N
wherein N is an integer more than the number of effective phials connected to one horizontal scanning line. Each of the N processor elements PE
1
to PE
N
processes video data corresponding to one of the pixels connected to one horizontal scanning line.
FIG. 32
illustrates a configuration of a conventional video signal processor
3100
. The video signal processor
3100
includes a data input register
3101
, an operator
3102
, and a data output register
3105
.
The data input register
301
outputs a plurality of serially input video data units to the operator
3102
in parallel. The data input register
3101
has a width of a bits and a depth of N words. The bit width a of the data input register
3101
is larger than a bit width of a general video signal to be processed. This is because there arises instances where a current luminance signal and a luminance signal delayed by one field must be input into the data input register
3101
simultaneously, for example.
The operator
3102
performs a predetermined arithmetic operation for the plurality of video data units output from the data input register
3101
in parallel. The operator
3102
includes N processor elements PE
1
to PE
N
. Each of the processor elements PE
1
to PE
N
includes a small-capacity memory
3103
which holds the input data and operation results and an operating element
3104
which performs a predetermined signal processing operation.
The data output register
3105
outputs the plurality of video data units processed by the operator
3102
in series. The data output register
3105
has a width of t bits and a depth of N words. The bit width t of the data output register
3108
is also larger than a bit width of a general video signal to be processed. This is because there arises instances where an output video signal and data relating to a motion delayed by one field must be output from the data output register
3105
simultaneously, for example.
Hereinbelow, the operation of the video signal processor
3100
will be described, taking as an example a process of removing a horizontal high frequency band component included in a video signal, i.e., a processing of performing horizontal low-pass filtering for a video signal (hereinbelow, referred to as an LPF processing).
FIG. 33
illustrates operations of the data input register
3101
, the operator
3102
, and the data output register
3105
in the LPF processing. In
FIG. 33
, the x-axis represents the time.
The video signal processor
3100
operates in accordance with a horizontal synchronous signal which defines horizontal blanking periods and effective video periods as shown in FIG.
33
.
During an effective video period
Akiyama Tsuyoshi
Miki Yoichiro
Miyaguchi Hiroshi
Ninomiya Kazuki
Sokawa Kenta
Matsushita Electric - Industrial Co., Ltd.
Ratner & Prestia
Yenke Brian P.
LandOfFree
Television receiver, video signal processing device, image... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Television receiver, video signal processing device, image..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Television receiver, video signal processing device, image... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2847356