Multiplex communications – Pathfinding or routing – Through a circuit switch
Reexamination Certificate
2000-07-20
2004-03-30
Vincent, David (Department: 2661)
Multiplex communications
Pathfinding or routing
Through a circuit switch
C370S537000
Reexamination Certificate
active
06714538
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to telephony switching apparatus and more particularly but not exclusively to apparatus for use with a cross-connect or like device for use in telephone switching.
BACKGROUND OF THE INVENTION
In a telephone network, individual telephone calls are digitized to form low level DS-0 channels which are then time domain multiplexed for transmission over digital lines. Different standards of multiplexing exist, with a North American standard containing 24 channels in its first order multiplexing signal, which is referred to as a DS-1 signal. In other parts of the world, most notably Europe, the CCITT standard is used in which the first order multiplex is called a CEPTI signal. The CEPTI signal contains between 30 and 32 DS-0 channels. At various points along the trunk there are what are known as 1/0 cross-connects which are provided in order to allow for rerouting of some of the DS-0 channels from one multiplex stream to another multiplex stream, for which access is required to the individual DS-0 channels.
In practice, the cross-connect is expected to handle large numbers of data streams in real time, and thus it often converts the serial data to an 8-bit or larger wide parallel stream for its own internal handling. In order to accomplish this with large numbers of input streams, very large numbers of serial to parallel shift registers are placed at the input and an equally large number of parallel to serial shift registers are placed at the output. For example, in order to handle 32 DS-1 data streams, each stream would require two shift registers that could be accessed in turn, giving a total of 64 shift registers. The large number of shift registers is expensive and may require use of more than one integrated circuit device. The need to use more than one integrated circuit is particularly disadvantageous.
SUMMARY OF THE INVENTION
According to a first aspect of the present invention there is provided apparatus comprising an input, a series of shift registers and an output, the input arranged to receive a plurality of serial data streams, each of the data streams containing groups of data, and to take simultaneously data bits from at least some of the plurality of data streams and to place the data bits into the series of shift registers, such that the data bits of a given bit position in the data groups of the some of the multiple data streams are placed together in one of the shift registers, and successive bits of a part of one of the data groups appear in a given data position across the shift registers, and the output being arranged to read out, in parallel, data of a given data position across the series of shift registers, simultaneously.
Preferably, the serial data streams are bundles of DS-1 signals and the data groups are DS-0 channels. In an embodiment there is further provided a demultiplexer for taking data bits simultaneously from at least some of the plurality of data streams and placing the data bits into the series of shift registers.
In one embodiment, a data buffer is placed at the input side of the series of shift registers. Preferably, the shift registers are set to operate at a first multiple greater than one of the speed at which the data groups are respectively able to provide the part of data at the input such that data of each channel can be removed from the bundle and reconstructed into the part of data in the shift registers and wherein the number of shift registers is less than the number of channels. Preferably this multiple is two. In an embodiment, the number of parallel streams is at least four.
In a particularly preferred embodiment, a number of shift registers in the series of shift registers is at most 16.
Preferably the apparatus is used to provide ports of a switching matrix. The port thus serves both as an input and an output port. There is provided a plurality of additional ports at other parts of the switching matrix, and the ports are connected via the switching matrix which is operable to switch individual words to any one of the ports according to an address. Preferably the port is also operable in reverse to bundle the parts of the data into data groups to form an output data stream.
According to a second aspect of the present invention there is provided a method of converting a plurality of serial data streams each carrying data groups into parts of the data groups arranged in parallel, the method comprising: receiving a plurality of serial data streams, each of the data streams containing groups of data, taking data bits simultaneously from at least some of the plurality of data streams, placing the data bits into a series of registers, such that the data bits of a given bit position in the data groups of the some of the multiple data streams are placed together in one of the registers, and successive bits of a part of one of the data groups appear in a given data position across the shift registers, and reading out, in parallel, data of a given data position across the series of shift registers, simultaneously.
Preferably, the data streams are bundles of DS-1 channels, the data groups are DS-0 channels, and each part of a data group is part of a DS-0 channel. The part of the data group referred to above is preferably a data word.
In a preferred embodiment the number of data streams is four and data may be input from the data streams at four times the rate of each stream.
The number of shift registers is preferably at most 16 if the number of DS-0 data channels is 64.
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Model PM 4344 and PM 6344 Deframer Catalogue, PMC-Sierra, Inc., Burnaby B.C., Canada, Oct. 1998.
Barash Amos
Jordan Reuven
Moshe Joseph
Silbiger Avi
Browdy and Neimark
ECI Telecom Ltd.
Vincent David
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