Coded data generation or conversion – Digital code to digital code converters – To or from nrz codes
Patent
1995-12-01
1997-08-12
Gaffin, Jeffrey A.
Coded data generation or conversion
Digital code to digital code converters
To or from nrz codes
341 68, H03M 512
Patent
active
056570171
ABSTRACT:
A signal converter for converting a bi-phase-level data stream to non-ret-to-zero-level data. The bi-phase-level data stream is input to a detector circuit. When the detector circuit detects a high level for more than half of a bit period, the detector circuit provides a logic zero pulse at a state S7. If the high level is not at the logic one state for a sufficient time period the detector circuit will not reach state s7. If the time period is to short than the detector circuit is reset to state s0. This high level pulse occurs whenever the second half of a bit period is high followed by a high in the first half of the following bit period. A sample is taken on the first half of every bit period. A low at the detector circuit keeps the detector circuit at state s0. A clock signal generating circuit receives the logic zero pulse and then proceeds through its states s0-s10. When state S1 is reached a clock pulse is provided by the clock signal generating circuit. This clock pulse is supplied to a Flip-Flop which also receives the bi-phase-level data stream. The clock pulse then clocks the logic level of the bi-phase-level data stream through the Flip-Flop to its output thereby providing a non-return-to-zero-level coded waveform or data stream.
REFERENCES:
patent: 4313103 (1982-01-01), Shull
patent: 4603322 (1986-07-01), Blair
patent: 5446765 (1995-08-01), Leger
patent: 5550864 (1996-08-01), Toy et al.
patent: 5602873 (1997-02-01), Balasubramanian et al.
Gaffin Jeffrey A.
Kalmbaugh David S.
Sliwka Melvin J.
The United States of America as represented by the Secretary of
Vick Jason H.
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