Telecommunications switch, multichannel facility datalink...

Multiplex communications – Pathfinding or routing – Through a circuit switch

Reexamination Certificate

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Details

C370S419000, C370S463000

Reexamination Certificate

active

06172975

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
This invention relates generally to telecommunications and more particularly to a telecommunications switch comprising a multichannel facility datalink processor and method of processing multiple facility datalink channels.
BACKGROUND OF THE INVENTION
In telecommunications equipment such as cross-connects, it is desirable for some applications to process a high number of high speed signals on a single circuit card. If many high speed signals can be processed by a single circuit card with reasonable power consumption and at reasonable cost, then the overall cost of the telecommunications switching equipment per channel may be reduced. Thus, in recent years, telecommunications equipment manufacturers have attempted to achieve higher density processing of telecommunications signals. Higher density processing allows more high speed telecommunication signals to be processed on a circuit board of a given size than was previously possible.
Many high speed telecommunications signals such as T
1
or DS
1
signals include a facility datalink signal. Facility datalink signals in a T
1
or DS
1
are typically four kilobit per second channels that are used for performance monitoring and high priority system messages between various pieces of telecommunication switching equipment. Facility datalink signals include HDLC formatted messages including 54016 messaging signals. Such signals are typically 14 byte signals comprising 8 data bytes, 2 address bytes, 2 CRC error correction code bytes, 1 byte of flag information, and 1 byte of control information. Such messages are sometimes referred to as PRM messages (performance report messages). Facility datalink signals may also use high priority messages known as BOM messages (bit oriented messages) which may contain a 1 byte abort signal and a 1 byte code message.
DSE or T
3
signals typically include 28 DS
1
s or 28 T
1
signals, respectively. Because each DS
1
or T
1
typically includes a facility datalink signal, processing a DSE or T
3
signal will also require the processing of 28 individual facility datalink signals. Producing high density circuit cards to process multiple facility datalinks thus presents a problem. The use of multiple integrated circuits each capable of processing only a single facility datalink may be impractical due to space on the printed circuit board, the cost of the integrated circuits and their power consumption.
One technique that can be used to process multiple versions of a communications signal with the same integrated circuit is to employ a state machine capable of processing one channel that is shared among multiple channels. Of course, such a circuit must operate fast enough to process all of the channels simultaneously. There is a trade-off between speed and the amount of circuitry required to process multiple signals simultaneously. Existing shared state machines will often load and unload the state associated with a particular channel in a round-robin fashion. Such loading and unloading of state information, however, may be inefficient if the signal does not need to be processed at the time that its state is loaded into the shared state machine.
In processing multiple communication channels, it is sometimes unnecessary to process certain signals on an ongoing basis. Performance monitoring information and error messages such as are provided by facility datalink signals may be received infrequently and at varying time intervals. Thus, it is desirable to interrupt a microprocessor controlling the system to process a facility datalink signal only when such a signal indicates that some intelligent processing is required by the telecommunications equipment. Efficiently interrupting the microprocessor may become difficult, however, when a large number of facility datalink signals are processed simultaneously. Thus, a novel method of alerting a processor that a particular datalink needs to be processed is needed.
SUMMARY OF THE INVENTION
One aspect of the invention is a multichannel facility datalink processor. The processor comprises input circuitry operable to receive a first plurality of facility datalink signals and output circuitry operable to output a second plurality of facility datalink signals. A state machine is operable to be loaded with a predetermined state and to process ones of the first plurality of facility datalink signals and ones of the second plurality of facility datalink signals. Storage circuitry is coupled to the state machine and is operable to store state information and facility datalink data for each of the first plurality of facility datalink signals and each of the second plurality of facility datalink signals.
The invention has several important technical advantages. The invention allows the processing both of facility datalink signals received and to be transmitted. The invention allows a microprocessor residing on a circuit card receiving a plurality of communication signals to process facility datalink channels only when they require service. The facility datalink processor employs a shared state machine that loads the state for a given facility datalink signal only when that signal requires processing. Because the invention reduces the overhead required to process multiple facility datalinks by reducing the amount of needless state information loaded into the state machine, throughput is improved and the processor may run at a lower clock speed. Running at a lower clock speed reduces the power consumption of the facility datalink processor. The invention allows multiple facility datalinks to be processed in a single integrated circuit at a reasonable cost, a reasonable power consumption, and with a reasonable amount of circuitry.


REFERENCES:
patent: 5526344 (1996-06-01), Diaz et al.
patent: 5689535 (1997-11-01), Cantwell et al.

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