Multiplex communications – Pathfinding or routing – Through a circuit switch
Reexamination Certificate
1998-06-22
2001-10-23
Hsu, Alpus H. (Department: 2662)
Multiplex communications
Pathfinding or routing
Through a circuit switch
C370S388000, C370S389000, C370S415000, C340S002240, C359S010000, C359S015000, C359S199200, C706S040000
Reexamination Certificate
active
06307854
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to the use of optical neural networks to control switches, in particular to the control of self-routing switches.
A switch is a device which takes N inputs and reproduces some or all of them at M outputs in some desired permutation. A switch may comprise a number of smaller switching elements which are connected together to form a larger switching function. A self-routing switch is one in which the route through the switch is not determined by a global controller but rather local routing decisions are made at each smaller switch element and therefore routing can take place very quickly.
In a packet switching network, information to be transmitted is digitised and then formed into small packets, each of which contains a destination address. The packets are transmitted over a communications network. The packets may be transmitted in asynchronous transfer mode (ATM) which is a standardised packet switching protocol.
If a switch can permute the inputs in any order then the switch is known as non-blocking, otherwise it is known as blocking. Two or more of the routes through a self-routing switch may overlap causing internal blocking. Prevention of internal blocking may be achieved either by sorting the packets so they start at different inputs, or by bypassing blocked packets, transmitting non-blocked packets which arrive at the switch after the blocked packets.
Hence, although a global controller is not needed in a self-routing switch for routing the individual packets a controller is still required to resolve potential blocking unless packets are to be lost.
It has been proposed to apply the techniques of neural networks to controlling signals in an ATM network. A general review is given in T X Brown, ‘Neural Networks for Switching’ from E C Posner, Ed, ‘Special Issue on Neural Networks in Communications’, IEEE Communications Magazine, p72, November 1989; see also
A Maren, C Hartson and R Rap, ‘Handbook of Neural Computing Applications’, Academic Press, London, 1990.
Artificial neural networks have been employed for many applications including pattern recognition and classification, content-addressable memory and combinatorial optimisation. For a general review, see J. Hertz, A. Krogh and R. G. Palmer, “Introduction to the theory of neural computation”, Addison-Wesley, Redwood City, Calif., 1991.
Electrical neural networks have been employed for control of a crossbar switch, see our patent application WO-A-94/24637, and for the control of self routing switches, see “Neural Network design of a Banyan network controller”, T. X. Brown & K. H. Lee, IEEJ on Selected Areas in Communications, Vol 8, No 8, pp 1428-1438,1990.
The individual neurons of a neural network may be connected together according to a number of different known schemes. They may be arranged in layers as in the case of a multi-layer perceptron, in which all the inputs to a given neuron are derived from the layer above. Another example is the Hopfield network, in which the neurons are mutually interconnected through neural weights. Many other connection schemes are well known in the art.
SUMMARY OF THE INVENTION
According to the invention there is provided a telecommunications switch comprising a switching device having a plurality of stages and control means for recognising routing requests which involve blocking of the switching device and including an optical neural network having a light source array to illuminate a photodetector array through a mask, each array having a respective array element for each possible path through the switching device, wherein the assignment of paths to array locations is such that, for the path corresponding to any light source array element, the photodetector array element positions corresponding to the paths blocked thereby form a pattern which is a shifted version of the pattern formed by the photodetector array elements corresponding to the paths blocked by a path corresponding to any other light source array element, whereby a single mask may be employed.
The switch may further comprise a plurality of buffers each with an input for receiving packets to be transmitted and an output line providing a source of packets to be switched.
The control means may be connected to receive destination addresses from packets stored in the buffer, to select packets which can be transmitted through the switching device without mutual blocking, and to release the selected packets from the buffers,
Preferably a packet is routed from a source line, identified by a binary source address, to a destination line, identified by a binary destination address; each stage of the switching device has a stage index, the last stage has its outputs connected to destination lines of the switch and has a stage index of zero, preceding stages have their outputs connected to inputs of the subsequent stage, and have a stage index equal to the stage index of the subsequent stage incremented by unity;
an output used by a packet after each stage is dependent on a predetermined source set of bits taken from the binary source address and a predetermined destination set of bits taken from the binary destination address;
the number of bits in the source set is equal to the stage index; and
the number of bits in the destination set is equal to the stage index subtracted from the total number of stages.
Preferably each of said stages has a plurality of switching elements, and each switching element has two inputs and two outputs and is operable in response to the binary destination address contained in a packet received by the element to route the packet to one or other output, the connection between the stages being such that each element of the first stage can serve any destination line, each element of any subsequent stage can serve a subset of the destination lines served by the stage which precedes it, each element in the last stage can serve any source line and each element of any preceding stage can serve a subset of the source lines served by the stage which follows it;
In a preferred embodiment of the invention
(i) the output of each element of the first stage has a destination index having a value of 0 or 1 according to whether it serves a first or a second partition of the destination lines;
(ii) the output of each element of each stage after the first has a destination index having a value of 0 or 1 according to whether it serves a first or a second partition of the destination lines served by those elements of the preceding stage to which the element in question is connected;
(iii) the input of each element of the last stage has a source index having a value of 0 or 1 according to whether it serves a first or a second partition of the source lines;
(iv) the input of each element of each preceding stage has a source index having a value of 0 or 1 according to whether it serves a first or a second partition of the source lines served by those elements of the following stage to which the element in question is connected;
(v) for each of said possible paths, the position in the respective array of the light source and of the photodetector which corresponds to that path is determined:
in a first co-ordinate direction, by a first co-ordinate having a magnitude equal to that represented by a binary number consisting of the destination indices of the element outputs traversed by that path, taken in the same order as the stages, with the index corresponding to an output from the first bank being the least significant bit and the index corresponding to an output from the last bank being the most significant bit; and
in a second co-ordinate direction, by a second co-ordinate having a magnitude equal to that represented by a binary number consisting of the source indices of the element inputs traversed by that path, taken in the same order as the stages with the index corresponding to an input to the first bank being the most significant bit and the index corresponding to an input to the last bank being the least significant bit.
According to another aspect of the invention
British Telecommunications public limited company
Hsu Alpus H.
Nixon & Vanderhye P.C.
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