Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
2006-07-26
2009-02-17
Vu, Hung (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S758000
Reexamination Certificate
active
07492030
ABSTRACT:
One aspect of the present subject matter relates to a method for forming an interlayer dielectric (ILD). In various embodiments of the method, an insulator layer is formed, at least one trench is formed in the insulator layer, and a metal layer is formed in the at least one trench. After the metal layer is formed, voids are formed in the insulator layer. One aspect of the present subject matter relates to an integrated circuit. In various embodiments, the integrated circuit includes an insulator structure having a plurality of voids that have a maximum size, and a metal layer formed in the insulator structure. The maximum size of the voids is larger than the minimum photo dimension of the metal layer such that a maximum-sized void is capable of extending between a first and second metal line in the metal layer. Other aspects are provided herein.
REFERENCES:
patent: 4962058 (1990-10-01), Cronin et al.
patent: 5461003 (1995-10-01), Havemann et al.
patent: 5847464 (1998-12-01), Singh et al.
patent: 6077792 (2000-06-01), Farrar
patent: 6100176 (2000-08-01), Forbes
patent: 6150257 (2000-11-01), Yin et al.
patent: 6208030 (2001-03-01), Tsui et al.
patent: 6309946 (2001-10-01), Givens
patent: 6387824 (2002-05-01), Aoi et al.
patent: 6395647 (2002-05-01), Li et al.
patent: 6413827 (2002-07-01), Farrar
patent: 6413852 (2002-07-01), Grill et al.
patent: 6420262 (2002-07-01), Farrar
patent: 6451712 (2002-09-01), Dalton et al.
patent: 6509590 (2003-01-01), Farrar
patent: 6522011 (2003-02-01), Farrar
patent: 6524944 (2003-02-01), Rangarajan et al.
patent: 6534835 (2003-03-01), Farrar
patent: 6537896 (2003-03-01), Catabay et al.
patent: 6541859 (2003-04-01), Forbes et al.
patent: 6573572 (2003-06-01), Farrar
patent: 6617239 (2003-09-01), Farrar
patent: 6630403 (2003-10-01), Kramer et al.
patent: 6649522 (2003-11-01), Farrar
patent: 6656822 (2003-12-01), Doyle et al.
patent: 6677209 (2004-01-01), Farrar
patent: 6774057 (2004-08-01), Lu et al.
patent: 6956289 (2005-10-01), Kunikiyo
patent: 7157387 (2007-01-01), Bhattacharyya et al.
patent: 7190043 (2007-03-01), Bhattacharyya et al.
patent: 2001/0014528 (2001-08-01), Clevenger et al.
patent: 2002/0014679 (2002-02-01), Lee et al.
patent: 2002/0168872 (2002-11-01), Farrar
patent: 2003/0015781 (2003-01-01), Farrar
patent: 2003/0127741 (2003-07-01), Farrar
patent: 2003/0181018 (2003-09-01), Geusic et al.
patent: 2004/0161922 (2004-08-01), Gallagher et al.
patent: 2005/0029609 (2005-02-01), Bhattacharyya et al.
Jin, C , “Evaluation of ultra-low-k dielectric materials for advanced interconnects”,Journal of Electronic Materials, 30(4), (Apr. 2001),284-9.
Pai, C S., et al., “A manufacturable embedded fluorinated SiO/sub 2/ for advanced 0.25 mu m CMOS VLSI multilevel interconnect applications”,Proceedings of the IEEE 1998 International Interconnect Technology Conference, (1998),39-41.
Saggio, M. , “Innovative Localized Lifetime Control in High-Speed IGBT's”,IEEE Electron Device Letters, 18(7), (1997),333-335.
Seager, C H., et al., “Electrical properties of He-implantation-produced nanocavities in silicon”,Physical Review B(Condensed Matter), 50(4), (Jul. 15, 1994),2458-73.
Tamaoka, E , et al., “Suppressing oxidization of hydrogen silsesquioxane films by using H/sub 2/O plasma in ashing process”,Proceedings of the IEEE 1998 International Interconnect Technology Conference, (1998),48-50.
Treichel, H , “Low dielectric constant materials”,Journal of Electronic Materials, 30(4), (Apr. 2001),290-8.
Weldon, M K., et al., “Mechanism of silicon exfoliation induced by hydrogen/helium co-implantation”,Applied Physics Letters, 73(25), (Dec. 21, 1998),3721-3.
Zhang, F , “Nanoglass/sup TM/ E copper damascene processing for etch, clean, and CMP”,Proceedings of the IEEE 2001 International Interconnect Technology Conference, (2001),57-9.
Bhattacharyya Arup
Farrar Paul A.
Micro)n Technology, Inc.
Schwegman Lundberg & Woessner, P.A.
Vu Hung
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