Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2002-01-18
2003-04-01
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185090, C365S185030
Reexamination Certificate
active
06542407
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to the field of data memories, and, more specifically, to memories of the type that store data as levels of electronic charge, including, but not limited to, flash electrically erasable and programmable read-only memories (flash EEPROMs) utilizing either conductive floating gates or dielectric material as charge storage elements.
BACKGROUND OF THE INVENTION
It is common in current commercial products for each storage element of a flash EEPROM array to store a single bit of data by operating in a binary mode, where two ranges of threshold levels of the storage element transistors are defined as storage levels. The threshold levels of transistors correspond to ranges of charge levels stored on their storage elements. In addition to shrinking the size of the memory arrays, the trend is to further increase the density of data storage of such memory arrays by storing more than one bit of data in each storage element transistor. This is accomplished by defining more than two threshold levels as storage states for each storage element transistor, four such states (2 bits of data per storage element) now being included in commercial products. More storage states, such as 16 states per storage element, are contemplated. Each storage element memory transistor has a certain total range (window) of threshold voltages in which it may practically be operated, and that range is divided into the number of states defined for it plus margins between the states to allow for them to be clearly differentiated from one another.
As the number of states stored in each memory cell increases, the tolerance of any shifts in the programmed charge level on the storage elements decreases. Since the ranges of charge designated for each storage stat necessarily be made narrower and placed closer together as the number of states stored on each memory cell storage element increases, the programming must be performed with an increased degree of precision and the extent of any post-programming shifts in the stored charge levels that can be tolerated, either actual or apparent shifts, is reduced. Actual disturbs to the charge stored in one cell can be created when programming and reading that cell, and when reading, programming and erasing other cells that have some degree of electrical coupling with the that cell, such as those in the same column or row, and those sharing a line or node.
Apparent shifts in the stored charge levels occur because of field coupling between storage elements. The degree of this coupling is necessarily increasing as the sizes of memory cell arrays are being decreased, which is occurring as the result of improvements of integrated circuit manufacturing techniques. The problem occurs most pronouncedly between two groups of adjacent cells that have been programmed at different times. One group of cells is programmed to add a level of charge to their storage elements that corresponds to one set of data. After the second group of cells is programmed with a second set of data, the charge levels read from the storage elements of the first group of cells often appear to be different than programmed because of the effect of the charge on the second group of storage elements being capacitively coupled with the first. This is known as the Yupin effect, and is described in U.S. Pat. No. 5,867,429, which patent is incorporated herein in their entirety by this reference. This patent describes either physically isolating the two groups of storage elements from each other, or taking into account the effect of the charge on the second group of storage elements when reading that of the first group.
In the types of memory systems described herein, as well as in others, including magnetic disc storage systems, the integrity of the data being stored is maintained by use of an error correction technique. Most commonly, an error correction code (ECC) is calculated for each sector or other unit of data that is being stored at one time, and that ECC is stored along with the data. The ECC is most commonly stored together with the sector of user data from which the ECC has been calculated. When this data is read from the memory, the ECC is used to determine the integrity of the user data being read. One or a few erroneous bits of data within a sector of data can often be corrected by use of the ECC but the existence of more errors renders the attempted data read to fail. Thus, the existence of bits that are read incorrectly because of close field coupling with adjacent memory cells can cause an attempted data read to fail.
SUMMARY OF THE INVENTION
In order to be able to recover valid data from a failed read of a first group of memory cells, as determined to have failed by the use of an ECC or otherwise, the data in at least an adjacent second group of memory cells, which are field coupled with the first group being read, are read and written elsewhere, either temporarily or permanently, followed by adjusting the programmed levels of the cells in the second group to that which allows the data originally written in the first group of cells to be accurately read. Ideally, the programmed levels of the second group of memory cells are returned to those existing when the first group of cells was programmed with the data that is now being read. The data is then accurately read from the first group since the fields coupled from the second group of cells are then the same as when the first group was programmed. But since it is often not practical to return the second group to the condition that existed when the first group was programmed, either because that initial condition is not known or for other reasons, the programmed levels of the cells of the second group are alternatively adjusted to a common level, usually the highest programmed level of the memory system.
The present invention can be implemented in various types of flash EEPROM cell arrays. A NOR array of one design has its memory cells connected between adjacent bit (column) lines and control gates connected to word (row) lines. The individual cells contain either one storage element transistor, with or without a select transistor formed in series with it, or two storage element transistors separated by a single select transistor. Examples of such arrays and their use in storage systems are given in the following U.S. patents and pending applications of SanDisk Corporation that are incorporated herein in their entirety by this reference: U.S. Pat. Nos. 5,095,344, 5,172,338, 5,602,987, 5,663,901, 5,430,859, 5,657,332, 5,712,180, 5,890,192, 6,091,633, 6,103,573 and 6,151,248, and applications Ser. No. 09/505,555, filed Feb. 17, 2000, Ser. No. 09/667,344, filed Sep. 22, 2000, Ser. No. 09/925,102, filed Aug. 8, 2001, and Ser. No. 09/925,134, filed Aug. 8, 2001.
A NAND array of one design has a number of memory cells, such as 8, 16 or even 32, connected in a series string between a bit line and a reference potential through select transistors at either end. Word lines are connected with control gates of cells across different series strings. Relevant examples of such arrays and their operation are given in the following U.S. patents and patent application that are incorporated herein in their entirety by this reference: U.S. Pat. Nos. 5,570,315, 5,774,397 and 6,046,935, and application Ser. No. 09/893,277, filed Jun. 27, 2001. Briefly, two bits of data from different logical pages of incoming data are programmed into one of four states of the individual cells in two steps, first programming a cell into one state according to one bit of data and then, if the data makes it necessary, re-programming that cell into another one of its states according to the second bit of incoming data.
The above-referenced patents and patent applications describe flash EEPROM systems that use conductive floating gates as memory cell storage elements. Alternatively, flash EEPROM systems with memory cells employing charge trapping dielectric material in place of floating gates are operated in substantially the same way. Examples
Chen Jian
Mak Alexander K.
Pham Long C.
Nguyen Tan T.
SanDisk Corporation
Skjerven Morrill LLP
LandOfFree
Techniques of recovering data from memory cells affected by... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Techniques of recovering data from memory cells affected by..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Techniques of recovering data from memory cells affected by... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3094880