Techniques for use with automated circuit design and...

Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C716S030000

Reexamination Certificate

active

07908574

ABSTRACT:
Various techniques related to clocking for use with automated circuit design and simulations are disclosed. In some embodiments, a method includes receiving descriptions of design circuitry including logic to receive input signals. The method further includes generating additional descriptions through at least one computer program including descriptions of a multiplexer to multiplex the input signals and delayed input signals, and provide them to the logic, and a demultiplexer to demultiplex output signals and delayed output signals from the logic. Other embodiments are described.

REFERENCES:
patent: 5596742 (1997-01-01), Agarwal et al.
patent: 5721890 (1998-02-01), Langendorf
patent: 5850537 (1998-12-01), Selvidge et al.
patent: 6618839 (2003-09-01), Beardslee et al.
patent: 6694464 (2004-02-01), Quayle et al.
patent: 6701491 (2004-03-01), Yang
patent: 6904576 (2005-06-01), Ng et al.
patent: 7072818 (2006-07-01), Beardslee et al.
patent: 7200822 (2007-04-01), McElvain
patent: 7213216 (2007-05-01), Ng et al.
patent: 7398445 (2008-07-01), Ng et al.
patent: 2002/0156614 (2002-10-01), Goode
patent: 2004/0222857 (2004-11-01), Adkisson
patent: 2005/0081113 (2005-04-01), Beard et al.
patent: 2006/0022724 (2006-02-01), Zerbe et al.
patent: 2006/0190860 (2006-08-01), Ng et al.
patent: 2006/0259834 (2006-11-01), Ng et al.
patent: 2008/0092001 (2008-04-01), Kodavalla et al.
patent: 1 441 296 (2004-07-01), None
patent: 10-0710972 (2007-04-01), None
patent: 10-0767957 (2007-10-01), None
patent: 10-0812938 (2008-03-01), None
PCT International Search Report and Written Opinion, PCT/US2008/006011, mailing date Mar. 17, 2009, 21 pages.
PCT Invitation to Pay Additional Fees, PCT/US2008/005989, Oct. 13, 2008, 6 pages.
PCT International Search Report and Written Opinion, PCT/US2008/005989, Dec. 29, 2008, 23 pages.
PCT Invitation to Pay Additional Fees, PCT/US2008/006011, Sep. 30, 2008, 6 pages.
PCT International Search Report and Written Opinion, PCT/US2008/006009, Sep. 25, 2008, 10 pages.
PCT Invitation to Pay Additional Fees, PCT/US2008/006012, Oct. 16, 2008, 6 pages.
Chuang, Chin-Lung, et al., “A Snapshot Method to Provide Full Visibility for Functional Debugging using FPGA,” Proceedings of the 13th Asian Test Symposium, IEEE Computer Society, Nov. 15, 2004, 6 pages.
Chuang, Chin-Lung, et al., “Hybrid Approach to Faster Functional Verification with Full Visibility,” IEEE Design & Test of Computers, Advances in Functional Validation through Hybrid Techniques, vol. 24, No. 2, Mar. 1, 2007, pp. 154-162.
Koch, Gernot, et al., “Debugging of Behavioral VHDL Specifications by Source Level Emulation,” Design Automation Conference, IEEE Computer Society, Sep. 18, 1995, pp. 256-261.
PCT International Search Report and Written Opinion, PCT/US2008/006012, Jan. 14, 2009, 21 pages.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Techniques for use with automated circuit design and... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Techniques for use with automated circuit design and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Techniques for use with automated circuit design and... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2707535

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.