Techniques for selecting phases of clock signals

Details Techniques for selecting phases of clock signals Techniques for selecting phases of clock signals

2009-02-27

2010-10-26

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S145000, C327S147000

Reexamination Certificate

active

07821312

ABSTRACT:
A clock signal generator circuit that receives periodic signals has a delay circuit, first and second multiplexers, and flip-flops. The delay circuit delays the periodic signals to generate delayed signals. The first multiplexer selects one of the delayed signals in response to a first select signal to generate an output clock signal. The second multiplexer selects one of the periodic signals in response to a second select signal. The flip-flops generate the first and the second select signals in response to the periodic signal selected by the second multiplexer.

REFERENCES:
patent: 6104228 (2000-08-01), Lakshmikumar
patent: 6933761 (2005-08-01), Chang
patent: 7378893 (2008-05-01), Kang
patent: 7453968 (2008-11-01), Chang et al.
patent: 2005/0200390 (2005-09-01), Starr et al.
patent: 2005/0259775 (2005-11-01), Chang et al.

Affiliated with

Also associated with

Rating

Techniques for selecting phases of clock signals does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Techniques for selecting phases of clock signals, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Techniques for selecting phases of clock signals will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4188098