Techniques for reticle layout to modify wafer test structure...

Details Techniques for reticle layout to modify wafer test structure... Techniques for reticle layout to modify wafer test structure...

2005-11-22

2005-11-22

Chambliss, Alonzo (Department: 2814)

Semiconductor device manufacturing: process

Including control responsive to sensed condition

Electrical characteristic sensed

C438S018000, C257S048000

Reexamination Certificate

active

06967111

ABSTRACT:
Techniques are provided for forming die on wafers with large area test structures between primary die. A reticle is used to pattern each die. The pattern on the reticle forms a primary die and test structures in scribelines that abut edges of the die. A reticle can be used to form additional test structures that are separated from the primary die. A gap is formed between the additional test structures and the primary die in each exposure. In subsequent exposures, test structures for adjacent die are formed in the gaps between the previously formed primary die and their additional test structures. These techniques are used to provide larger test structure area between each primary die. A blade can be used to block portions of the reticle that form the additional test structures. The reticle can then be used to pattern die with smaller test structures during high volume chip production.

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