Techniques for reducing leakage current in memory devices

Details Techniques for reducing leakage current in memory devices Techniques for reducing leakage current in memory devices

2007-07-17

2010-06-29

Lam, David (Department: 2827)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S229000, C365S222000, C365S189110

Reexamination Certificate

active

07746720

ABSTRACT:
Techniques for reducing gate induced drain leakage (GIDL) in memory devices utilizing negative wordline architectures. More specifically, a method and apparatus are provided to determine whether any of the word lines in a section of a memory array are active. If any one of the plurality of word lines is active, each of the inactive word lines in the section are coupled to a negative voltage level. If none of the plurality of word lines is active, each of the plurality of word lines is coupled to ground to reduce GIDL.

REFERENCES:
patent: 5532971 (1996-07-01), Tanaka et al.
patent: 5617369 (1997-04-01), Tomishima et al.
patent: 5684317 (1997-11-01), Hwang
patent: 6219297 (2001-04-01), Cho et al.
patent: 6370069 (2002-04-01), Brass et al.
patent: 6693012 (2004-02-01), Mouli et al.
patent: 6862236 (2005-03-01), Maruyama

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